optimize verilog file

software: leonardo;

input: s1238.v, moduleDFF;

output: s1238_opt.v

Note: *** Theoretically this step is not needed, since we already have the valid circuit Verilog description. Because some of the circuit elements are not supported in Leonardo, the original Verilog file has to go through "check" step. That translates, the output is the  Verilog file with the same functionality, which is guaranteed to work in the further synthesis process.

see file tree

1)add DFF module to verilog file

-open s1238.v

-delete note part "//..."

-copy moduleDFF at the top of file

(notice that there are many different ways to describe the DFF function. Either structural or behavior model can be employed. )

-save s1238.v

2)optimize verilog file

-run leonardo (command "leonardo")

-load library (ASIC/ADK/AMI 0.5 micron fast)

(other advanced technology libraries can be chosen to match the design. )

-read verilog file (s1238.v)


-output verilog file (s1238_opt.v)