This tutorial shows the Application Specific Integrated Circuit (ASIC) design flow from netlist to layout. The complete design flow will take the input netlist files, i.e., VHDL or Verilog hardware definition files, and generates the output file that includes the physical layout information, which is to be used in IC fabrication. Our tutorial is the step by step process showing our course design project on a ISCAS89 full scan circuit S1238. This course was directed by Dr. Nelson during Spring 2004.


The major steps in the whole design include: netlist synthesis using Leonardo, scan-chain insertion using DFTAdvisor, netlist to schematic conversion from EDIF file to EDDM schematic and the IC layout using adk_ic tools. During the whole process, design & test steps are iterated concurrently to improve the whole project o meet our goal, which is to fabricate a test chip to verify a new delay fault test method. The chip is to be fabricated through MOSIS using AMI05 technologies.


The content of the tutorial is categoried based on the major processes involved. For each section, the real screen fastshot is captured combined with text description to illustrate the whole process.


Schematic generation:

Given a circuit netlist file, which is usually in VHDL or Verilog format, an internal EDIF file is required to be generated for further producing circuit schematic. The tool that is used in this step is Leonardo. Since scan chain is desired to provide testability to the manufactured chips. DFTAdvisor is also used.


Note: the synthesizable Verilog grammar is not the same as Verilog file that is used for simulation purpose. For example, the nmos element is not supported in Leonardo. Thus, the original Verilog file with D FlipFlop (DFF) that is described using nmos sentences has to be modified to meet this requirement.


Notice that Leonardo can take both structural or behavior description of the circuits. The circuit s1238 that we used includes both behavior and structural descriptions.