-- mips_memory_bin.vhd
--   1K x 32 word-addressable memory model
--   Address bits 1-0 are ignored
--   Memory is loaded at startup with the contents
--      of file "testprog"
--   "testprog" is assumed to contain lines of 32-bit binary no's

library ieee;
use ieee.std_logic_1164.all;
use work.qsim_logic.all;             -- for to_integer function
use std.textio.all;                  -- For file operations

entity mips_memory_bin is
 port(dbus:  inout std_logic_vector(31 downto 0); -- 32-bit data bus
      abus:  in    std_logic_vector(11 downto 0); -- 12-bit address input
      rd,wr: in    std_logic);                    -- active-high read/write enable
end mips_memory_bin;

architecture m1 of mips_memory_bin is
begin

-- The memory array is managed by this one process
mem: process(rd,wr,abus,dbus)
    
    type memory is array (natural range <>) of std_logic_vector(31 downto 0);
    variable M:     memory(0 to 2**10-1);               -- actual storage array
    variable iaddr: integer;                            -- integer version of address
    variable init:  boolean := true;                    -- true at start of simulation
    file P:         text open read_mode is "testprog";  -- program object code file
    variable LN:    line;                               -- temp variable for file read
    variable LB:    bit_vector(31 downto 0);
    variable i:     natural := 0;

begin

    -- Do this only at simulation start to load a "program" into memory
    if init then
       while not endfile(P) loop        -- Read program from data file
          readline(P,LN);               -- Read one line of the file
          read(LN,LB);                  -- Convert to bit_vector
          M(i) := to_stdlogicvector(LB);      -- Put in M as std_logic_vector
	  i := i + 1;
       end loop;
       init := false;                        -- Disable memory load
     end if;
  
   iaddr := to_integer('0' & to_bitvector(abus(11 downto 2)));  -- convert upper 10 address bits to integer
   
   -- Disable data bus driver unless doing a read
   if rd = '0' then
      dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";   -- float the data bus
   end if;
 
   -- Memory read if rd = 1
   if rd = '1' then
      dbus <= M(iaddr);    -- Memory data onto data bus 
   
   -- Memory write if wr = 1
   elsif wr = '1' then
       M(iaddr) := dbus;        -- Store data in memory
   end if;
   
end process;

end;