Recent Talks and Papers of
Vishwani D. Agrawal
My talks:
VLSI D&T Seminar (Spring'14), March 5, 2014, Specification Test Minimization for Given Defect Level (LATW'14 talk)
VLSI D&T Seminar (Spring'13), April 3, 2013, A Test Time Theorem and Its Applications (LATW'13 talk)
Invited Talk at NYU-AB, April 15, 2011: Testing for Faults, Looking for Defects
Talk at Virginia Tech, June 2, 2009: Daignostic Test Generation
VLSI D&T Seminar (Fall'07), Effectiveness Measures for VLSI Testing: Defective Parts per Million, Defect Coverage and Fault Coverage
VLSI D&T Seminar (Fall'07), Using Hierarchy in Design Automation: The Fault Collapsing Problem (VDAT'07)
VLSI D&T Seminar (Spring'07), Delay Test Quality Evaluation using Bounded Gate Delays (VTS'07)
VLSI D&T Seminar (Fall'06), Upper Bounding Fault Coverage in Stafan (VTS'06)
VLSI D&T Seminar (Spring'06), Multi-Core Parallelism for Low-Power Design
Talk at Texas Instr., Bangalore, Dec. 29, 2005, Concurrent Test Generation
VLSI D&T Seminar:
Implication Graphs (Spring'05)
,
Spectral Testing (Fall'04)
Distinguished Lecture Series (2005), Rutgers University
,
Talk Abstract
slides
VLSI Design'19:
. . .
Energy Efficient Power Distribution on Many Core SoC, by Shihab and Agrawal
. . .
Two-Pattern Delta-IDDQ Test for Recycled IC Detection, by Chowdhury, Guin, Singh and Agrawal
VDAT'18:
VLSI Design and Test - A Keynote Talk, by Agrawal
,
slides
VTS'18:
Modeling and Test Generation for Combinational Hardware Trojans, by Zhou, Guin and Agrawal
JETTA
, vol. 33, no. 5, Oct 2017, pp. 573-589,
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects, by B. Zhang and V. D. Agrawal
JETTA
, vol. 33, no. 2, Apr 2017, pp. 171-187,
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling, by V. Sheshadri, V. D. Agrawal and P. Agrawal
VTS'16:
. . .
Characterizing Processors for Energy and Performance Management (Poster), by Goyal and Agrawal
. . .
Failure Evasion: Statistically Solving the NP Complete . . . Testing Difficult-to-Detect Faults (EJM PhD Thesis Competition), by Venkatasubramanian and Agrawal
poster
NATW'16:
Failures Guide Probabilistic Search for a Hard-to-Find Test (pp. 18-23), Venkatasubramanian and Agrawal
slides
NCUR'16:
Analytical Delay and Variation Modeling in Subthreshold Region, by Kim and Agrawal
slides
JETTA
, vol. 32, no. 2, Apr 2016, pp. 209-225,
Applications of Mixed-Signal Technology in Digital Testing, by Li and Agrawal
VLSI Design'16:
Database Search and ATPG - Interdisciplinary Domains and Algorithms, An Embedded Tutorial (pp. 38-43), by Venkatasubramanian and Agrawal
slides
MTV'15:
Characterizing Processors for Energy and Performance Management, by Goyal and Agrawal
slides
ATS'15:
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key (pp. 91-96), by Liu and Agrawal
slides
DFT'15:
Quest for a Quantum Search Algorithm for Testing Stuck-at Faults in Digital Circuits (pp. 128-133), by Venkatasubramanian and Agrawal
slides
JETTA
, vol. 31, no. 5, Oct 2015, pp. 479-489,
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests, by Sindia and Agrawal
JETTA
, vol. 31, no. 4, Aug 2015, pp. 403-410,
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing, by Gunasekar and Agrawal
NATW'15:
. . .
Multivalued Logic for Reduced Pin Count and Multi-Site SoC Testing (pp. 49-54), by Li and Agrawal
slides
. . .
SoC TAM Design to Minimize Test Application Time (pp. 55-60), by Zhang and Agrawal
slides
LATS'15:
Adopting Multi-Valued Logic for Reduced Pin-Count Testing, by Li, Zhang and Agrawal
slides
VLSI Design'15:
. . .
Diagnostic Tests for Pre-Bond TSV Defects (pp. 387-392), by Zhang and Agrawal
slides
. . .
Few Good Frequencies for Power-Constrained Test (pp. 393-398), by Gunasekar and Agrawal
slides
JOLPE
, vol. 10, no. 4, Dec 2014, pp. 617-628,
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design, by Jayaraman and Agrawal
JETTA
, vol. 30, no. 6, Dec 2014, pp. 763-780,
Diagnostic Test Generation for Transition Delay Faults Using Stuck-at Fault Detection Tools, by Y. Zhang, B. Zhang and Agrawal
ICCD14:
An Optimized Diagnostic Procedure for Pre-Bond TSV Defects (pp. 189-194), by B. Zhang and Agrawal
S3S14:
An Optimal Probing Method of Pre-Bond TSV Fault Identification in 3D Stacked ICs (3 pages), by B. Zhang and Agrawal
NATW'14:
. . .
Testing With Reduced ATE Channels (6 pages), by Li, Zhang and Agrawal
slides
. . .
A New Test Vector Search Algorithm for a Single Stuck-at Fault using Probabilistic Correlation (pp. 57-60), by Venkatasubramanian and Agrawal
slides
. . .
Selecting ATE Frequencies for Power Constrained Test Time Reduction Using Aperiodic Clock (pp. 52-56), by Gunasekar and Agrawal
slides
VTS14:
. . .
Elevator Talk: DPPM for Analog and RF Circuits, by Agrawal and Sindia
. . .
ATE Test Time Reduction by Scaling Supply Voltage and Frequency (EJ McCluskey Best PhD Thesis Candidate), by Venkataramani and Agrawal
slides
JETTA
, vol. 30, no. 2, Apr 2014,
A Test Time Theorem and its Applications (pp. 229-236), by Venkataramani, Sindia and Agrawal
LATW'14:
Specification Test Minimization for Given Defect Level (6 pages), by Sindia and Agrawal
slides
JETTA
, vol. 30, no. 1, Feb 2014,
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs (pp. 57-75), by Zhang and Agrawal
S3S'13
:
Dual-Threshold Design of Sub-threshold Circuits (pp. 77-78), by Yao and Agrawal
slides
3DIC'13
:
Yield Analysis of a Novel Wafer Manipulation Method in 3D Stacking (8 pages), by Zhang, Li and Agrawal
VLSI-SoC'13
:
Power-Aware SoC Test Optimization through Dynamic Voltage and Frequency Scaling (pp. 105-110), by Sheshadri, Agrawal and Agrawal
slides
JOLPE
, vol. 9, no. 3, pp. 275-287, Oct 2013,
Energy-Efficient Dual-Voltage Design Using Topological Constraints, by Allani and Agrawal
ITC'13:
. . .
High Sensitivity Test Signatures for Unconventional Analog Circuit Test Paradigms (Paper PTF1-EJ McCluskey Best PhD Thesis Finalist), by Sindia and Agrawal
slides
. . .
ATE Test Time Reduction Using Asynchronous Clocking (Paper 15.3), by Venkataramani and Agrawal
slides
JETTA
, vol. 29, no. 4, pp. 473-483, Aug 2013,
Neural Network Guided Spatial Fault Resilience in Array Processors, by Sindia and Agrawal
VDAT'13:
Defect Diagnosis of Digital Circuits Using Surrogate Faults (pp. 376-386), by Alagappan and Agrawal
slides
DAC'13:
An Analog Bus for Low Power (Poster), by Taher, Sindia and Agrawal
NATW'13:
. . .
Sessionless SoC Test Scheduling With Frequency Scaling, by Sheshadri, Agrawal and Agrawal
slides
. . .
Test Programming for Power Constrained Devices, by Venkataramani and Agrawal
slides
. . .
Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults, by Alagappan and Agrawal
slides
. . .
Wafer Cut and Rotation for Compound Yield Improvement in 3D Wafer-on-Wafer Stacking, by Zhang and Agrawal
VTS'13:
Finding Best Voltage and Frequency to Shorten Power-Constrained Test Time (pp. 19-24), by Venkataramani, Sindia and Agrawal
slides
LATW'13:
A Test Time Theorem and Its Applications (5 pages), by Venkataramani, Sindia and Agrawal
slides
SSST'13:
. . .
Managing Performance and Efficiency of a Processor (pp. 59-62), by Shinde and Agrawal
slides
. . .
MobSched: Customizable Scheduler for Mobile Cloud Computing (pp. 129-134), by Sindia, Gao, Black, Lim, Agrawal and Agrawal
slides
JETTA
, vol. 29, no. 1, pp. 103-114, Feb 2013,
Eliminating the Timing Penalty of Scan, by Sinanoglu and Agrawal
VLSI Design'13:
. . .
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages (pp. 267-272), by Sheshadri, Agrawal and Agrawal
slides
. . .
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage (pp. 273-278), by Venkataramani and Agrawal
slides
JETTA
, vol. 28, no. 6, pp. 869-875, Dec 2012,
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB, by Chakraborty and Agrawal
ATS12:
Tailoring Tests for Functional Binning of Integrated Circuits, by Sindia and Agrawal
slides
ITC12:
. . .
Elevator Talk: Reduced Voltage Test Can be Faster! by Agrawal
. . .
Reducing ATE Time for Power Constrained Scan Test by Asynchronous Clocking, by Venkataramani and Agrawal
poster
JETTA
, vol. 28, no. 5, pp. 757-771, Oct 2012,
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients, by Sindia, Agrawal and Singh
SOCC2012:
Optimal Power-Constrained SoC Test Schedules With Customizable Clock Rates, by Sheshadri, Agrawal and Agrawal
slides
JETTA
, vol. 28, no. 4, pp. 541-549, Aug 2012,
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing, by Sindia, Agrawal and Singh
Heritage Institute of Technology, Kolkata:
Power and Time Tradeoff in VLSI Testing, Invited Talk by Agrawal, July 13, 2012
Texas Instruments, Bangalore:
Synchronous Versus Asynchronous Testing, by Agrawal, July 11, 2012
VDAT'12:
. . .
Analog and RF Circuit Testing - Education Day Talk, by Sindia and Agrawal
. . .
Power Problems in VLSI Circuit Testing (pp. 393-405), by Rashid and Agrawal
slides (Keynote Talk)
DFM&Y'12:
Test-Time Reduction in ATE Using Asynchronous Clocking, by Venkataramani and Agrawal
poster
ISCAS'12:
Impact of Process Variations on Computers Used for Image Processing, by Sindia, Dai, Agrawal and Singh
slides
video
NATW'12:
. . .
Optimizing Fault Coverage for Error Resilient Applications: An Integer Linear Programming Formulation (7 pages), by Sindia and Agrawal
. . .
Weighted Random and Transition Density Patterns For Scan-BIST (8 pages), by Rashid and Agrawal
slides
VTS'12:
. . .
Net Diagnosis Using Stuck-at and Transition Fault Models (pp. 221-226), by Zhao and Agrawal
slides
. . .
Towards Spatial Fault Resilience in Array Processors (pp. 288-293), by Sindia and Agrawal
LATW'12:
. . .
Retiming Scan Circuit to Eliminate Timing Penalty (pp. 137-142), by Sinanoglu and Agrawal
slides
. . . Pre-Computed Asynchronous Scan (Invited Talk), by Agrawal
slides
JETTA
, vol. 28, no. 2, pp. 177-187, Apr 2012,
Diagnostic Test Set Minimization and Full-Response Fault Dictionary, by Shukoor and Agrawal
SSST'12:
. . .
An Efficient Algorithm for Dual-Voltage Design without Need for Level Conversion (pp. 51-56), by Allani and Agrawal
slides
. . .
All-Digital Replica Techniques for Managing Random Mismatch in Time-to-Digital Converters (pp. 130-134), by Sindia, Dai and Agrawal
VLSI Design'12:
. . .
Keynote: A History of the VLSI Design Conference (pp. 1-2), by Agrawal
slides
. . .
Externally Tested Scan Circuit With Built-In Activity Monitor and Adaptive Test Clock (pp. 448-453), by Shanmugasundaram and Agrawal
slides
JOLPE
, vol. 7, no. 4, pp. 460-470, Dec 2011,
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply, by Kim and Agrawal
ATS11:
Test and Diagnosis of Analog Circuits using Moment Generating Functions (pp. 371-376), by Sindia, Agrawal and Singh
slides
ICCD11:
Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis (pp. 96-101), by Zhang and Agrawal
slides
VDAT11:
Architectural Power Management for Battery Lifetime Optimization in Portable Systems, by Kulkarni and Agrawal
slides
NATW11:
. . .
LNA Test: A Polynomial Coefficient Approach, by Sindia, Agrawal and Dai
slides
. . .
Diagnostic Test Generation and Fault Simulation Algorithms for Transition Faults (7 pages), by Zhang and Agrawal
slides
VTS'11:
. . .
Non-Linear Analog Circuit Test and Diagnosis under Process Variation using V-Transform Coefficients (pp. 64-69), by Sindia, Agrawal and Singh
slides
. . .
Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit (pp. 248-253), by Shunmugasundaram and Agrawal
slides
. . .
An Efficient Test Data Reduction Technique through Dynamic Pattern Mixing across Multiple Fault Models (pp. 285-290), by Alampally, Venkatesh, Shanmugasundaram, Parekhji and Agrawal
slides
LATW11:
. . .
Keynote Talk: Testing for Faults, Looking for Defects, by V. D. Agrawal
. . .
Testing Linear and Non-Linear Analog Circuits using Moment Generating Functions, by Sindia, Agrawal and Singh
slides
ISQED'11:
Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates (pp. 689-694), by Kim and Agrawal
slides
ICIT'11:
Dual Voltage Design for Minimum Energy Using Gate Slack (pp. 419-424), by Kim and Agrawal
slides
SSST'11:
. . .
Architectural Power Management for High Leakage Technologies (pp. 67-72), by Kulkarni, Sheth and Agrawal
slides
. . .
Energy Source Lifetime Optimization for a Digital System through Power Management (73-78), by Kulkarni and Agrawal
slides
. . .
Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance (pp. 98-103), by Venkatasubramanian and Agrawal
slides
. . .
A DSP-Based Ramp Test for On-Chip High-Resolution ADC (pp. 203-207), by Jiang and Agrawal
slides
. . .
Distinguishing Process Variation Induced Faults from Manufacturing Defects in Analog Circuits using V-Transform Coefficients (pp. 231-236), by Sindia, Agrawal and Singh
slides
. . .
Dynamic Scan Clock Control in BIST Circuits (pp. 237-242), by Shanmugasundaram and Agrawal
slides
RASDAT'11:
Dynamic Scan Clock Control in BIST Circuits (pp. 25-30), by Shanmugasundaram and Agrawal
slides
VLSI Design'11:
True Minimum Energy Design Using Dual Below-Threshold Supply Voltages (pp. 292-297), by Kim and Agrawal
slides
ITC10:
A Diagnostic Test Generation System, by Zhang and Agrawal (Paper 12.3)
slides
VDAT10:
A Tutorial on Battery Simulation - Matching power Source to Electronic System, by Kulkarni and Agrawal
slides
ETS10:
A Diagnostic Test Generation System and a Coverage Metric, by Zhang and Agrawal
poster
NATW10:
A Diagnostic Test Generation System (9 pages), by Zhang and Agrawal
slides
LATW10:
An Algorithm for Diagnostic Fault Simulation (pp. 1-5), by Zhang and Agrawal
slides
VTS'10:
Application of Signal and Noise Theory to Digital VLSI Testing (pp. 215-220), by Yogi and Agrawal
slides
ISQED'10:
Soft Error Rate Determination for Nanoscale Sequential Logic (pp. 225-230), by Wang and Agrawal
SSST10:
. . .
Enhancing Random Access Scan for Soft Error Tolerance (pp. 263-268), by Wang and Agrawal
,
slides
. . .
Soft Error Considerations for Computer Web Servers (pp. 269-274), by Wang and Agrawal
,
slides
VLSI Design'10:
. . .
Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients (pp. 288-293), by Sindia, Singh and Agrawal
slides
. . .
Low Power CMOS Design (Education Forum Presentation), by Agrawal
ATS'09:
Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients (pp. 63-68), by Sindia, Singh and Agrawal
WICAT-NSF Review, UVA, Nov 19-20, 2009:
Low Power Design of CMOS VLSI Circuits, by V. D. Agrawal
IEEE-TVLSI, vol. 17, no. 10, pp. 1534-1545, Oct. 2009,
Variable Input Delay CMOS Logic for Low Power Design, by Raja, Agrawal and Bushnell
EWDTS'09:
V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-Linear Analog Circuits (pp. 283-286), by Sindia, Singh and Agrawal
slides
VDAT'09:
. . .
BIST/Test-Decompressor Design using Combinational Test Spectrum (pp. 443-454), by Yogi and Agrawal
slides
. . .
Bounds on Defect Level and Fault Coverage in Analog Circuit Testing (pp. 410-421), by Sindia, Singh and Agrawal
slides
WICAT-NSF Review, Virginia Tech, June 1-2, 2009:
Poster by Jiang and Agrawal
slides
handout
ISCAS'09:
Designing Variation-Tolerance in Mixed-Signal Components of a System-on-Chip, by Jiang and Agrawal
slides
ETS'09:
. . .
On Minimization of Peak Power for Scan Circuit during Test (pp. 25-30), by Tudu, Larsson, Singh and Agrawal
. . .
A Two Phase Approach for Minimal Diagnostic Test Set Generation (pp. 115-120), by Shukoor and Agrawal
slides
ISVLSI'09:
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations, by Alexander and Agrawal
slides
NATW'09:
. . .
Built-in Adaptive Test and Calibration of DAC (pp. 3-8), by Jiang and Agrawal
slides
. . .
Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits (pp. 9-18), by Sindia, Singh and Agrawal
slides
. . .
Compaction of Diagnostic Test Set for a Full-Response Dictionary, by Shukoor and Agrawal
slides
GLSVLSI'09:
Polynomial Coefficient Based DC Testing of Non-Linear Analog Circuits, by Sindia, Singh and Agrawal
slides
VTS'09:
Output Hazard-Free Transition Delay Fault Test Generation, by Menon, Singh and Agrawal
SSST'09:
Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation, by Alexander and Agrawal
slides
VLSI Design'09:
Soft Error Rates with Inertial and Logical Masking, by Wang and Agrawal
slides
ATS'08:
Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns, by Yogi and Agrawal
slides
ITC'08:
Built-In Self-Calibration of On-Chip DAC and ADC, by Jiang and Agrawal
ISLPED'08: A Tutorial on Test Power, by Agrawal,
abstract page
,
slides
VDAT'08:
....
Naresh Malipeddi Remembered
....
A Primal-Dual Solution to Minimal Test Generation Problem, by Shukoor and Agrawal
slides
....
Tutorial: RFIC Design and Testing for Wireless Communications, by Agrawal and Dai (pdf, 2.5MB)
Abstract
NATW'08:
....
Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, by Jiang and Agrawal
slides
....
Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation, by Grimes and Agrawal
slides
....
Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters, by Wang and Agrawal
slides
....
Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns, by Yogi and Agrawal
slides
VTS'08:
Fault Nodes in Implication Graphs . . . , by Sethuram, Bushnell and Agrawal
slides
SSST'08:
....
N-Model Tests for VLSI Circuits, by Yogi and Agrawal
slides
....
Soft Error Rate Determination for Nanometer CMOS VLSI Circuits, by Wang and Agrawal
slides
VLSI Design'08:
....
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation, by Lu and Agrawal
slides
....
Single Event Upset: An Embedded Tutorial, by Wang and Agrawal
slides
ITC'07:
....
Fault Simulation With Bounded Gate Delay Model, by Bose, Grimes and Agrawal
slides
....
Estimating Stuck Fault Coverage in Sequential Logic Using State Traversal and Entropy Analysis, by Bose and Agrawal
slides
....
SPARTAN: A Spectral and Information Theoretic Approach to Partial Scan, by Khan, Bushnell, Devanathan and Agrawal
T-VLSI
, vol. 15, no. 11, pp. 1245-1255, Nov. 2007,
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss, by Rao, Bushnell and Agrawal
VDAT'07:
Using Hierarchy in Design Automation: The Fault Collapsing Problem, by Sandireddy and Agrawal
slides
NATW'07:
Optimizing Tests for Multiple Fault Models, by Yogi and Agrawal
slides
VTS'07:
Delay Test Quality Evaluation using Bounded Gate Delays, by Bose and Agrawal
slides
SSST'07:
Transition Delay Fault Testing of Microprocessors by Spectral Method, by Yogi and Agrawal
slides
VLSI Design'07:
....
A Reduced Complexity Algorithm for Minimizing N-Detect Tests, by Kantipudi and Agrawal
slides
....
Statistical Leakage and Timing Optimization for Submicron Process Variation, by Lu and Agrawal
slides
....
Spectral RTL Test Generation for Microprocessors, by Yogi and Agrawal
slides
JOLPE
, vol. 2, no. 3, pp. 378-387, Dec 2006,
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff, by Lu and Agrawal
ATS'06,
Spectral RTL Test Generation for Gate-Level Stuck-at Faults, by Yogi and Agrawal
slides
ITC'06,
Fault Coverage Estimation for Non-Random Functional Input Sequences, by Bose and Agrawal
slides
ISLPED'06,
Input-Specific Dynamic Power Optimization for VLSI Circuits, by Hu and Agrawal
slides
VDAT'06:
....
Tutorial: Low-Power Electronics and Systems, by Agrawal (118 slides)
....
Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests, by Yogi and Agrawal
slides
NATW'06,
High-Level Test Generation for Gate-Level Fault Coverage, by Yogi and Agrawal
slides
JOLPE
, vol. 2, no. 1, pp. 121-128, Apr 2006,
Transistor Sizing of Logic Gates to Maximize Input Delay Variability, by Raja, Agrawal and Bushnell
VTS'06:
Upper Bounding Fault Coverage . . . , by Agrawal, Bose and Gangaram
slides
VLSI Design'06:
On the Size and Generation of Minimal N-Detection Tests, by Kantipudi and Agrawal
slides
ATS05:
Concurrent Test Generation, by Agrawal and Doshi
slides
ITC05:
A Random Access Scan Architecture . . ., by Mudlapur, Agrawal and Singh
slides
ICCD05:
Enhanced Dual-Transition Probabilistic Power Estimation . . ., by Hu and Agrawal
slides
PATMOS05:
....
Variable Input Delay CMOS Logic . . ., by Raja, Agrawal and Bushnell
slides
....
Leakage and Dynamic Glitch Power . . ., by Lu and Agrawal
slides
VDAT05:
....
Glitch-Free Design of Low Power ASICs . . ., by Uppalapati, Bushnell and Agrawal
slides
....
A Novel Random Access Flip-Flop Design, by Mudlapur, Agrawal and Singh
slides
....
Independence Fault Collapsing, by Doshi and Agrawal
slides
NATW05:
Use of Hierarchy in Fault Collapsing, by Sandireddy and Agrawal
slides
GLS-VLSI05:
Dual-Transition Glitch Filtering . . . , by Hu and Agrawal
(poster)
DATE05:
Diagnostic and Detection Fault Collapsing . . . , by Sandireddy and Agrawal
slides
Talk on Low-Power Design at TI (1/12/05) and Intel (1/13/05)
slides
abstract
IEEE-TCAD
, vol. 24, no. 6, pp. 948-956, June 2005, with Kim and Saluja:
....
"Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits"
IEEE-TCAD
, vol. 22, no. 8, pp. 1104-1113, Aug. 2003, with Thaker and Zaghloul:
....
"A Test Evaluation Technique for VLSI Circuits Using Register-Transfer Level Fault Modeling"
VLSI Design'04 Paper, A Tutorial on the Emerging Nanotechnology Devices,
ps
pdf
ppt
VLSI Design'03 Papers, January 6-8, 2003:
.... Exclusive Test and its Applications to Fault Diagnosis,
Paper (pdf)
,
Talk (ppt)
.... New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss,
Paper (pdf)
,
Talk (ppt)
ITC'02: Analog Macromodeling of Capacitive Coupling Faults ...
pdf
IEEE-Electron Device/Solid-State Bangalore Section Talks, Aug 23, 2002:
....
Minimum Dynamic Power CMOS Circuits, 26 slides (ppt)
....
Fundamentals of Testing and DFT, 85 slides (ppt)
IEEE Bangalore Section Talks, January 16, 2002:
....
Delay Testing of Digital Circuits (15 ppt slides)
....
High-Speed VLSI Testing with Slow Test Equipment (13 ppt slides)
VLSI Design'02 Paper:
Multiple Faults: Modeling, Simulation and Test (pdf)
....
18 ppt slides
VLSI Design'02 Tutorial, Electronic Testing for SOC Designers, Jan. 8, 2002:
284 ppt slides*
.... *An abbreviated version of the complete
VLSI Testing Course
High-Speed VLSI Testing with Slow Test Equipment, Lab Review, June 5, 2001:
....
3 ppt slides (summary)
....
14 ppt slides (full talk)
Mixed-Signal Test and DFT, Allentown Meeting, May 17, 2001:
43 ppt slides
ATS00 Keynote: Testing in the Fourth Dimension:
Talk astract (text)
/
Slides (ppt)
VLSI Design'95 Keynote:
Science, Technology, and the Indian Society
Selected Research Items of
Vishwani D. Agrawal
A Novel Clocking Technique for VLSI Circuit Testability,
JSSC, vol. 19, pp. 207-212, Apr 1984, paper by Mercer and Agrawal (pdf, 1MB)
Polynomial time solvable fault detection problems,
FTCS'90 paper by Chakradhar, Agrawal and Bushnell (pdf, 2.6MB)
Entropy-based statistical design verification,
FTCS'82 paper by Seth and Agrawal (pdf, 2.8MB)
An Information Theoretic Approach to Digital Fault Testing,
Paper in IEEETC (pdf, 5.26MB)
Predict - Probabilistic Controllability and Observability Algorithms:
Paper in Integration J. (pdf, 1.5MB)
Still Unpublished:
Antitest, Exclusive Test and Concurrent Test
with
Kewal Saluja
CE Education:
Test in VLSI Design Course
Report
/
Cost of Education
/
Interdisciplinary CE Curriculum
Delay Test:
Optimistic Update Theorem (Bose)
,
IMTC99 Savir Paper
,
ATS98 False Path Removal Paper
,
ITC98 PDF Simulation Paper
Fault Collapsing: ITC02
pdf
ppt
/ ITC03
pdf
ppt
/ VDAT03
doc
ppt
/ DATE05
pdf
ppt
/
MS Thesis
ppt
High-Level Testing:
Astract (doc)
Slides (ppt)
/ ITC'00
pdf
/
Thaker's Thesis (pdf)
High-Speed Test:
VDAT'00 talk powerpoint
, with
C. G. Parodi
Low-Power Design:
Talk astract (text)
/
Slides (ppt)
/ Paper 1
ps
pdf
/ Paper 2
ps
pdf
/ Paper 3
pdf
ppt
. . . Paper 4
ps
pdf
ppt
/ Paper 5
pdf (unpublished)
/ Raja's Theses, MS
pdf
, PhD
pdf
ppt
/ Siri's MS Thesis
pdf
ppt
. . . Paper 6
pdf
ppt
/ FeiHu's PhD
Thesis
Defense
Redundancy Identification: ATS'96
pdf
/ My talk
ppt
/ DELTA'02
pdf
ppt
/ VLSI Design'03
pdf
ppt
. . . NATW'03
pdf
ppt
/ Manuscript
pdf
/ NATW'04
pdf
/
Dave's MS Thesis
/ VLSI Design'05
pdf
ppt
Spectral Methods in Testing: DATE'01
pdf
, with
Michael Hsiao
. . .
VTS'01 paper
/
ATS'00 paper (doc)
/
VLSI Design'02 Tutorial (ppt)
/
ITC'04 paper
Test Generation: VLSI Design'01 paper
pdf
ppt
, ITC'01 paper
pdf
, with
Y. Kim
and
K. Saluja
Verification:
AT&T Test Conf.'95
/
VLSI Design'96
/ VLSI Design'00 Paper
pdf
VLSI Test Quality and Coverage:
Fault Occurrence Probability
/ DATE'00
pdf
/ ITSW'01
ppt
/ NATW'01
pdf
/ LATW'11
ppt
/
JETTA
'12
pdf
See
Bibliography 1968-1980
for Early Work on Antennas & Microwaves or
the Full Bibliography
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