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Homework 1: Introduction and ATE (Due Feb 8, 2002)

Problems 1.1, 1.3, 2.2 and 2.4;

Homework 2: Economics, Yield and Fault Modeling (Due Feb 15, 2002)

Problems 3.1, 3.7, 4.7, 4.8 and 4.10;

Homework 3: Simulation (Due Mar 1, 2002)

Write a true-value logic simulation program for combinational circuits. Represent signals by two-state (0,1) logic. The inputs to the program are: (1) an input vector file, (2) flat circuit description in the Rutmod format, and (3) a user-supplied list of signals (default primary outputs) for which simulated values are desired. The output of the program should be a table of signal values. Use your program to verify the design of a four-bit ripple-carry adder using the vectors of Table 5.1. Execute the following steps: (a) Manually compute the output of each vector (b) Run simulator to verify that your circuit produces correct outputs (c) Diagnose a netlist encoding error - In the verified circuit, change one gate (e.g., replace AND by OR). Starting from an incorrect PO, examine signal values until you locate the error. Prepare a report (no longer than 5 pages) on program (algorithm, user manual), and the results of (a), (b) and (c). Program listing can be attached and can be in addition to 5 pages.

Homework 4: Testability Measures (Due Mar 1, 2002)

Problems 6.4, 6.6 and 6.10;

Homework 5: Combinational ATPG (Due Mar 8, 2002)

Problems 7.1, 7.4, 7.8, 7.10 and 7.23;

Homework 6: Sequential Circuit ATPG (Due Mar 15, 2002)

Problems 8.14 and 8.17;

Homework 7: Memory Test (Due Mar 29, 2002)

Problems 9.4, 9.7, 9.9 and 9.23;

Homework 8: Analog Test (Due Apr 5, 2002)

Problems 10.4, 10.12, 10.14 and 11.4;

Homework 9: Delay Test and IDDQ Test (Due Apr 12, 2002)

Problems 12.2, 12.4 and 13.3

Homework 10: Scan Design (Due Apr 19, 2002)

Problems 14.2, 14.3 and 14.4;

Homework 11: BIST (Due Apr 26, 2002)

Problems 15.7, 15.10 and 15.23;

Homework 12: Boundary Scan and Analog Test Bus (Due May 3, 2002)

Problems 16.1, 16.3, 16.9 and 17.1;

Homework 13: System Test and Core-Based Design (Due May 10, 2002)

Problems 18.1 and 18.3;