ELEC7250-001 VLSI Testing (Spring 2005)
Tuesday/Thursday, 11:00AM-12:15PM, Broun 235
Assigned 3-10-05, to be completed 4-7-05
1. Each student should select a separate project.
2. Examine the problem, study literature, sketch a solution, identify tasks, and create
a project plan with a time schedule for completion.
3. Submit a one-page project plan (a list of tasks with completion dates) by 3-17-05.
4. Programs should be written such that they can be compiled and run by others. User
interface should be simple and intuitive.
5. AUSIM (see Lecture 0) and Hitec/Proofs (Homework 7) can be used.
6. Project report should contain:
(a) Abstract - Problem solved, main ideas, sample results.
(b) Introduction - Problem explained, background surveyed, organization of the report.
(c) Analysis and algorithms (use simple examples for illustrations).
(d) Results - user information, example results, inferences.
(e) Conclusion - Accomplishments, lessons learned, suggested improvements.
Project 1: Derive tests for ISCAS'85 (combinational) and ISCAS'89 (sequential) circuits
and display test length, fault coverage and CPU time as functions of number of
gates and number of flip-flops. State any conclusions from the data about the
test complexity. (Cheng) (due 4/14/05, extended deadline due to problem change.)
Project 2: Write a test pattern generation program using the Podem algorithm. (Dhingra)
Project 3: Write a test pattern generation program for generating a single test vector
for a combinational circuit to detect all (or most) faults from a given set.
Project 4: Derive and program a new ATPG algorithm for combinational circuits using
four-state logic (0, 1, D, D-bar). Start with an arbitrary fully-specified
input vector and then modify it to detect a target fault. Verify your vectors
using the AUSIM or Proofs fault simulator. (Kantipudi)
Project 5: Write a parallel fault simulator for sequential logic circuits. (Maddela)
Project 6: Write a program to compute SCOAP testability measures. Develop an ATPG strategy
by targeting a sample of faults consisting of most difficult to test faults.
Project 7: Parallelize an ATPG program to run on a distributed system of computers and
evaluate the speedup as a function of the number of processors. (Han)
Project 8: Write a logic simulator and use it to compact a set of random vectors to
maximize the activity (entropy) at the circuit output. Using a fault simulator
determine whether the compacted vectors are better or worse than random vectors.
Project 9: Develop a fault diagnosis procedure. Using a complete set of vectors examine how
well your procedure identifies single and multiple stuck-at faults in the 4-bit
ALU circuit. (Ray)
Project 10: Add hardware to the sequential benchmark circuit s5378 to make it scan testable.
Generate combinational vectors, convert them into scan sequences and simulate
faults in the sequential mode. (Sinha)
Project 11: Implement circular self-test in the sequential benchmark circuit s5378. Using a
fault simulator find the fault coverage for 10,000 clock cycles. (Vemula)