Tuesday/Thursday, 11:00AM-12:15PM, Broun 235

Course Syllabus, Syllabus Slides, Grades: tabulation graph

FINAL EXAM (25%): April 30, 2005, 2:00-4:30PM, Broun 306

The idea of a focused preparation is not to narrow down the scope of the course. The student remains responsible for all 18 chapters of the textbook and all 23 lectures. However, the following list is given to make the preparation for the final exam manageable. Questions will be based on:

1. Stuck-at faults, equivalence, indistinguishability.

2. SCOAP combinational testability measures.

3. ATPG concepts, time-frame expansion, parallel fault simulation.

4. Diagnostic fault dictionary and diagnostic tree.

5. Full scan concepts, test length.

Use of books and notes during the exam will be permitted.

Instructor: Professor Vishwani D. Agrawal, vagrawal@eng.auburn.edu, Broun 323, 334-844-1853.

Text book:

Library research contact: Andy Wohrley, Engineering Librarian, wohrlaj@auburn.edu, 844-1768, or just look for Andy in the library.

HOMEWORK (30%):

Homework 1 -- Problems 1.1 and 1.5, assigned 1/20/05, due 2/3/05

Homework 2 -- Problems 3.1 and 3.6, assigned 1/27/05, due 2/10/05

Homework 3 -- Problems 4.9 and 4.10, assigned 2/3/05, due 2/17/05

Homework 4 -- Problems 5.2, 5.11, 5.17 and 5.26, assigned 2/10/05, due 2/24/05

Homework 5 -- Problems 6.3 and 6.8, assigned 2/17/05, due 3/3/05

Homework 6 -- Problems 7.3 and 7.5, assigned 2/24/05, due 3/10/05

Homework 7 -- Derive the smallest test set to detect all faults of a four-bit ALU (netlist, schematic). You may use the Hitec/Proofs/Atalanta programs (user's manual, setup procedure) available on ECE computers. Document your procedure and results. Remember that known test sets of 12 vectors exist for this circuit. Assigned 3/10/05, due 3/24/05. Solution: see research paper.

Homework 8 -- Problems 8.9 and 8.12, assigned 3/17/05, due 4/7/05

Homework 9 -- Problems 9.1, 9.6 and 9.11, assigned 3/24/05, due 4/14/05

Homework 10 -- Problems 12.1 and 13.1, assigned 4/7/05, due 4/21/05

Homework 11 -- Problems 14.5, 14.6 and 15.10, assigned 4/14/05, due 4/28/05 (IF OVERDUE, PLEASE SUBMIT ASAP)

PROJECT (25%), assigned 3/10/05, project plan due 3/17/05, completion report due 4/7/05.

TERM PAPERS (10%), assigned 4/5/05, due 4/19/05.

CLASS PRESENTATION (Slides 5%, Talk 5%):

4/26/05 Cheng, Dhingra, Han, Kantipudi, Maddela, Prasad

4/28/05 Raghuraman, Ramamurthy, Ray, Sinha, Vemula

Instructions: 1. Select a topic based on your project or term paper.

2. Email 5-8 (including title and conclusion) slides at least one hour before the class. Talk time must not exceed 12 minutes.

Slide 1 -- Title

Slide 2 -- Problem statement

Slide 3 -- Background work, including most relevant references

Slides 4-5 -- Main ideas, analysis, algorithms

Slides 6-7 -- Results and inferences

Slide 8 -- Conclusion

REPORTS (IF OVERDUE, PLEASE SUBMIT ASAP):

Cheng: Project (Test Complexity) Paper (Multiple Fault Diagnosis) Slides (Diagnosis)

Dhingra: Project (Podem) Paper (LFSR and CA) Slides (LFSR and CA)

Han: Project (Distributed ATPG) Paper (SIC Delay Test) Slides (Distributed ATPG)

Kantipudi: Project (ATPG) Paper (Testability Measures) Slides (Testability Measures)

Maddela: Project (Parallel Seq. Fsim) Paper (Recursive Learning) Slides (Recursive Learning)

Prasad: Project (SCOAP) Paper (Proofs) Slides (Proofs)

Raghuraman: Project (ATPG) Paper (Memory Test) Slides (ATPG)

Ramamurthy: Project (Entropy) Paper (Random Access Scan) Slides (Entropy)

Ray: Project (Diagnosis) Paper (Statistical Fault Simulation) Slides (Diagnosis)

Sinha: Project (Scanning s5378) Paper (Neural Network ATPG) Slides (Neural Net ATPG)

Vemula: Project (Circular BIST) Paper (Scan-Based Delay Test) Slides (Delay Test Flip-Flop)

LECTURES:

Lecture 0: AUSIM and HDL 1/11/05 and 1/13/05 Guest lectures by Prof. C. E. Stroud

Lecture 1: Introduction, 1/18/05

Lecture 2: Test Process and ATE, Chapter 2 (reading assignment 1/20/05)

Lecture 3: Test Economics, 1/20/05

Lecture 4: Yield Analysis and Product Quality, 1/25/05

Lecture 5: Fault Modeling, 1/27/05

Lecture 6: Logic Simulation, 2/1/05

Lecture 7: Fault Simulation, 2/3/05 and 2/8/05

Lecture 8: Testability Measures, 2/10/05 and 2/15/05

Lecture 9: Combinational ATPG Basics, 2/17/05 and 2/22/05

Lecture 10: Redundancy Removal Using ATPG, 2/22/05

Lecture 11: Major Combinational ATPG Algorithms, 2/24/05 and 3/1/05

Lecture 12: Advanced Combinational ATPG Algorithms, 3/3/05 and 3/8/05

Lecture 13: Seq. Circuit ATPG -- Time-Frame Expansion, 3/10/05

Lecture 14: Seq. Circuit ATPG -- Simulation-Based Methods, 3/15/05

Lecture 15alt: Memory Test, 3/17/05

Lecture 16alt: Memory NPSF and Parametric Test, 3/22/05 Hamiltonian path in action

Lecture 17alt: Analog Test and IEEE 1149.4 Standard, 4/19/05

Lecture 18alt: Delay Test, 3/24/05

Lecture 19alt: IDDQ Testing, 4/5/05

Lecture 20alt: Design for Testability (DFT) - Full Scan, 4/7/03

Lecture 21alt: DFT - Partial, Random-Access and Boundary Scan, 4/12/05

Lecture 22alt: BIST - Built-In Self-Test, 4/14/05

Lecture 23alt: System Test, 4/21/05