E7250 Class Projects (Spring 2004)
Assigned 02-26-04, to be completed 03-25-04
1. Form a team of 1 to 5 members and select any one project.
2. Examine the problem, study literature, sketch a solution, identify tasks
and assign to team members, and create a project plan with a time schedule
3. Submit a one-page project plan (title, team members, and list of tasks with completion dates) by 03-09-04.
4. Following items are available:
(a) c17.bench, a small circuit netlist for program debugging.
(b) 74181.bench, a larger circuit netlist to demonstrate results.
(c) Circuit diagrams (MSWord):
(d) Hitec, an ATPG program on ECE Unix computers.
(e) Proofs, a fault simulator program in the Hitec package on ECE Unix computers.
(f) Hitec and Proofs user manual: ps
5. Programs should be written such that they can be compiled and run by
others. User interface should be simple and intuitive.
6. Project report should contain:
(a) Abstract - Problem solved, main ideas, sample results.
(b) Introduction - Problem explained, background surveyed, organization of
(c) Analysis and algorithms (use simple examples for illustrations).
(d) Results - user information, example results, inferences.
(e) Conclusion - Accomplishments, lessons learned, suggested improvements.
Project 1: Write a program for dominance fault collapsing. Compare the sizes
of the dominance and equivalence collapsed fault sets. Compare
the Hitec ATPG results for the two collapsed fault sets.
Project 2: Write a program to obtain probabilistic testability for all
stuck-at faults in a combinational circuit (see reference ).
List 10% of most difficult to test faults. Examine an ATPG
strategy in which the most difficult faults are targeted first.
Project 3: Write a fault simulator for combinational circuits using the
parallel pattern single fault propagation (PPSFP) method (see
reference ). Using your simulator develop a random pattern
ATPG system. Verify results with the Proofs fault simulator.
Project 5: Invent a new ATPG algorithm for combinational circuits using four-
state logic (0, 1, D, D-bar). Start with an arbitrary fully-
specified input vector and then modify it to detect a target
fault. Verify your result using the Proofs fault simulator.
Project 6: Write a program to count the total number of the paths in a
combinational circuit and find the critical path(s). Have your
program generate a two-vector path delay test to robustly test a
critical path. See Chapter 12 and reference .