ELEC 6270-001/ELEC 5270-001 Low-Power Design of Electronic Circuits
Spring 2015, MWF 2PM, Broun 235
Course Syllabus, Grade Sheet

Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE

CLASS TEST: Friday, March 20, 2015, Broun 235, 2:00PM - 2:50PM, books, notes, computer, etc., permitted
FINAL EXAM: Tuesday, May 5, 2013, Broun 235, 4:00PM - 6:30PM, books, notes, computer, etc., permitted

ANNOUNCEMENTS:
4/17/15 Course evaluation open until May 3. Questions?

HOMEWORK:
Homework 1, assigned 2/9/15, due 2/16/15, An LP solver
Homework 2, assigned 3/11/15, due 3/18/15
Homework 3, assigned 4/19/15, due 4/27/15

PROJECT:

Assignment 4/13/14, final report due 5/1/15
Report (by email), 4-6 pages in two-column publishable paper format (Credit: 10 points for 6270, 25 points for 5270)
Slides (five max, by email), 6270 only
Class presentation (5 minutes), 6270 talk (10 points), 5270 attendance, April 25, 27, May 1
Note: Project grade for 5270-001 is based on the report and attendance in talks; slides and presentation are optional.

A useful lecture on CAD tools: Tools for Power Analysis by Murali Dharan
A 4-bit Adder Example: Spice netlist, Input vectors
Email questions about CAD tools, etc.

5270 Project Reports: 1 2 3 4
6270 Project Reports: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

LECTURES:

Lecture 1: Introduction to Low Power Design, 1/14/15 . . .
Lecture 2: Power Dissipation of CMOS Circuits, 1/21/15 . . .
Lecture 3: Power Analysis, 1/28/15 . . .
Lecture 4: Linear Programming, 2/9/15 . . .
LP Solvers:
. . . PHPSimplex Online Solver
. . . LINDO Download
Lecture 5: Gate-Level Power Optimization, 2/18/15 . . .
Lecture 6: Test Power, 2/27/15 . . .
Lecture 7: Energy Source Design, 3/11/15 . . .
Lecture 8: Power Aware Microprocessors, 3/18/15 . . .
Lecture 9: Memory and Multicore Design, 4/8/15 . . .
Lecture 10: Adiabatic Logic, 4/13/15 . . .
Lecture 11: Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic, 4/17/15 . . .
Lecture 12: Pass Transistor Logic: A Low Power Logic Family, 4/20/15 . . .

READING ASSIGNMENTS:
Device Scaling:
1/18/15: M. Bohr, "A 30 Year Retrospective on Dennard's MOSFET Scaling Paper".
1/18/15: 1974 paper by Dennard et al.
Power Constrained Test:
2/27/15: Y. Bonhomme, et al., "Power Driven Chaining of Flip-Flops in Scan Architectures,” Proc. International Test Conf., 2002, pp. 796–803.
2/27/15: V. Sheshadri, et al., "Optimal Power-Constrained SoC Test Schedules With Customizable Clock Rates,” Proc. 25th IEEE International System-on-Chip Conf., 2012, pp. 271–276.
2/27/15: V. Sheshadri, et al., "Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages,” Proc. 26th International Conf. on VLSI Design, Jan 2013, pp. 267–272.
2/27/15: P. Venkataramani, et al., "A Test Time Theorem and Its Applications,” Journal of Electronic Testing: Theory and Applications, vol. 30, no. 2, pp. 229–236, Apr 2014.
Managing Power Source:
3/11/15: R. W. Erikson, "DC-DC Power Converters," Wiley Encyclopedia of Electrical and Electronics Engineering.
3/11/15: M. Chen and G. A. Rincon-Mora, "Accurate Electrical Battery Model . . . ," IEEE Trans. Energy Conversion, vol. 21, no. 2, pp. 504-511, June 2006.
3/11/15: M. Kulkarni and V. D. Agrawal, "Energy Source Lifetime Optimization . . . ," Proc. SSST, Auburn, Mar 14-16, 2011, pp. 75-80.
3/11/15: M. Kim et al., "Measuring Variance Between Smartphone Energy Consumption and Battery Life," Computer, vol. 47, pp. 59-65, July 2014.
Power Management of Processors:
3/18/15: T. Sakurai, "Alpha Power-Law Model," IEEE Solid-State Circuits Society Newsletter, vol. 9, no. 4, pp. 4-5, Oct. 2004.
3/18/15: A. Shinde and V. D. Agrawal, "Managing Performance and Efficiency of a Processor," Proc. 45th SSST, Mar 11, 2013, pp. 59-62.
Multicore Power:
4/8/15: D. H. Woo and H.-H. S. Lee, "Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era," Computer, vol. 41, no. 12, pp. 24-31, Dec 2008.
Adiabatic Logic and Energy Recovery:
4/13/15: A. G. Dickinson and J. S. Denker, "Adiabatic Dynamic Logic," IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, Mar 1995.
4/13/15: Read about recycling of clock energy in "Good Timing," IEEE Spectrum, vol. 49, no. 7, pp. 11-12, July 2012.
Pass Transistor Logic:
4/20/15: R. Zimmermann and W. Fichtner, "Pow-Power Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.

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