####################
#       SETUP      #
#################### 

set sh_enable_page_mode true
set power_enable_analysis TRUE
set power_analysis_mode time_based


set link_path {/linux_apps/cadence_libs/vtvt_tsmc250_release_4/Synopsys_Libraries/libs/vtvt_tsmc250.db}

set search_path {. ./../src ./../reports/ }


read_verilog ripple_adder_1.v

current_design ripple_adder

link_design
####################
#    CONSTRAIN     #
#################### 

check_timing

create_clock -period 1000 -name VCLK 

set_input_delay 0 -clock VCLK [all_inputs]
set_output_delay 0 -clock VCLK [all_outputs]

check_timing


####################
#  ENV ATTRIBUTES  #
#################### 
#1. 
set_driving_cell -lib_cell inv_1 [all_inputs]

#2.
set_load -pin_load 1 [all_outputs]

#3. 
set_wire_load_model -name 05x05 

#4.
set_operating_conditions -library vtvt_tsmc250 -analysis_type single WCCOM


###############
#   REPORT	   #
###############
read_vcd -zero_delay ripple_adder_dump.vcd -strip_path tb_ripple_adder/DUT
#read_vcd -zero_delay -rtl ripple_adder_dump.vcd -strip_path tb_ripple_adder/DUT

check_power
update_power
report_power 
report_power  > ./power_report.rpt  
report_timing -path_type full -delay_type max -max_paths 2 > ./timing_report.rpt 

####################
#      CLEANUP     #
#################### 

#1.
remove_design -all

#2.
remove_lib -all