------------------------------------------------------------
-- VHDL code for a Register file with 'inr' and 'outvalue' 
-- created on : 28th Jan, 2009
-- contact    : Manish(mmk0002@auburn.edu)
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity regfile is
port(
     clock    : in std_logic;
     regwr    : in std_logic;
--   reset    : in std_logic;
     wrreg    : in std_logic_vector(3 downto 0);
     rr1      : in std_logic_vector(3 downto 0);
     rr2      : in std_logic_vector(3 downto 0);
     wrdata   : in std_logic_vector(15 downto 0);
     rd1      : out std_logic_vector(15 downto 0);   
     rd2      : out std_logic_vector(15 downto 0);
     inr: in std_logic_vector(3 downto 0);
     outvalue: out std_logic_vector(15 downto 0)	  
    );
end regfile;

architecture rtl of regfile is
type regs is array(0 to 15) of std_logic_vector(15 downto 0);
signal reg : regs;
 
begin
process(clock,wrdata,regwr)

begin

-- if initialisation of register file on 'reset' is required then uncomment the following lines and reset signal in the entity
-- if (reset = '0') then
-- reg(0)<= "0000000000000000";
-- reg(1)<= "0000000000000000";
-- reg(2)<= "0000000000000000";
-- reg(3)<= "0000000000000000";
-- reg(4)<= "0000000000000000";
-- reg(5)<= "0000000000000000";
-- reg(6)<= "0000000000000000";
-- reg(7)<= "0000000000000000";
-- reg(8)<= "0000000000000000";
-- reg(9)<= "0000000000000000";
-- reg(10)<= "0000000000000000";
-- reg(11)<= "0000000000000000";
-- reg(12)<= "0000000000000000";
-- reg(13)<= "0000000000000000";
-- reg(14)<= "0000000000000000";
-- reg(15)<= "0000000000000000";
-- elsif
if clock'event and clock = '1' then
 if regwr = '1' then
   if (wrreg = "0000") then
    reg(conv_integer('0' & wrreg)) <= "0000000000000000"; -- Register 0 hardwired to zero.
   else
    reg(conv_integer('0' & wrreg)) <= wrdata;
   end if;
 end if;
end if;

end process;

rd1 <= reg(conv_integer('0' & rr1));
rd2 <= reg(conv_integer('0' & rr2));

process (inr,reg)
    begin
case inr is
when  "0000" =>  outvalue<=reg(0);-- used to display the contents of the registers on FPGA in the final part.
when  "0001" =>	outvalue<=reg(1);
when  "0010" =>	outvalue<=reg(2);
when  "0011" =>	outvalue<=reg(3);
when  "0100" =>	outvalue<=reg(4);
when  "0101" =>	outvalue<=reg(5);
when  "0110" =>	outvalue<=reg(6);
when  "0111" =>	outvalue<=reg(7);
when  "1000" =>	outvalue<=reg(8);
when  "1001" =>	outvalue<=reg(9);
when  "1010" =>	outvalue<=reg(10);
when  "1011" =>	outvalue<=reg(11);
when  "1100" =>	outvalue<=reg(12);
when  "1101" =>	outvalue<=reg(13);
when  "1110" =>	outvalue<=reg(14);
when  "1111" =>	outvalue<=reg(15);
when others => outvalue<="0000000000000000";
  
end case;
end process;
end rtl;