Previous BIST Dudes and Dudettes
Graduate Students:
Bradley Dutton, Embedded Soft-Core Processor-Based
Built-In Self-Test of Field Programmable Gate Arrays, AU MSEE thesis,
2010, Auburn University Outstanding MS Student
for 2008-09
soon to be working for Intel in sunny (and hot) AZ
Qin,
Dutton & Stroud, On-Line Single Event Upset Detection and Correction in Field Programmable Gate Arrays, ISCA International J. on Computers & Their Applications, 2010
Dutton & Stroud, Soft-Core Embedded Processor-Based Built-In Self-Test of FPGAs: A Case Study, IEEE Southeast Symp. on System Theory, 2010
Dutton, Lerner, Vemula & Stroud, On System-Level Use of BIST for Programmable Input/Output Buffers in FPGAs, Proc. IEEE Southeast Regional Conf, 2010
Stroud & Dutton, The First Clock Cycle is a Real BIST, Proc. International Conf. on Embedded Systems and Applications, 2010
Dutton & Stroud, Soft Core Embedded Processor Based Built-In Self-Test of FPGAs, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009
Starr, Qin, Dutton, Stroud, Dai & Nelson, Automated Generation of BIST and Measurement Circuitry for Mixed-Signal Circuits and Systems, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009
Dutton, Ali, Stroud & Sunwoo, Embedded Processor Based Fault Injection and SEU Emulation for FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Dutton & Stroud, Built-in Self-test of Embedded SEU Detection and Correction Cores in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Dutton & Stroud, Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs, Proc. ISCA International Conf. on Computers and Their Applications, 2009
Dutton & Stroud, Built-In
Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs, Proc. IEEE
Dutton & Stroud, Built-In
Self-Test of Programmable Input/Output Tiles in Virtex-5 FPGAs, Proc. IEEE
Dutton, Lerner
& Stroud, Built-In Self-Test of Programmable I/O Cells in Virtex-4
FPGAs, Proc.
IEEE
Justin Dailey, Analysis and Implementation of Built-In
Self-Test Block Random Access Memories in Virtex-5 Field Programmable Gate
Arrays, AU MSEE thesis, 2011
currently working for National Instruments in sunny TX
Dailey, Garrison, Pulukuri & Stroud, Built-In Self-Test of Embedded Memory Cores in Virtex-5 Field
Programmable Gate Arrays, Proc.
Lusco, Dailey & Stroud, Built-In Self-Test for Multipliers in
Cyclone II Field Programmable Gate Arrays, Proc. IEEE
Neil Da Cunha, Built-In
Self-Test Configuration Generation for Field
Programmable Gate Arrays, AU MSEE project, 2011
Stroud & Da Cunha, Built-In Self-Test of Programmable Clock Buffers in Virtex-4, Virtex-5 and Virtex-6 FPGAs, Proc. Southeastern Symp. on System Theory, 20111
Bobby Dixon, Built-In Self-Test of the Programmable
Interconnect in Field Programmable Gate Arrays, AU MSEE thesis, 2008
currently working for the
Navy in sunny
Dixon & Stroud, Analysis
and Evaluation of Routing BIST Approaches for FPGAs, Proc. IEEE
Sachin Dinghra, Built-In Self-Test of Logic Resources in
Field Programmable Gate Arrays Using Partial Reconfiguration, AU MSEE
thesis, 2006
currently working at Altera
in sunny CA
Milton, Dhingra & Stroud, Embedded Processor Based BIST and Diagnosis of Logic and Memory Resources in FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2006
Dhingra, Milton & Stroud, BIST of Logic and Memory Resources in
Virtex-4 FPGAs, Proc. IEEE
Dhingra, Garimella,
Newalkar & Stroud, Built-In Self-Test for Virtex and Spartan II FPGAs Using Partial Reconfiguration,
Proc. IEEE
Srinivas Garimella, Built-In Self-Test of Embedded Memory
Cores in System-on-Chip Implementations, AU MSEE thesis, 2005, Auburn University Outstanding MS Student for 2004-05
currently working at Altera
in sunny CA
Stroud & Garimella, Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs, Proc. International Conf. on Embedded Systems and Applications, 2005
Dhingra, Garimella, Newalkar & Stroud, Built-In
Self-Test for Virtex and Spartan II FPGAs Using
Partial Reconfiguration, Proc. IEEE
Sunwoo, Garimella &
Stroud, On Embedded Processor
Reconfiguration of Logic BIST for FPGA Cores in SoCs,
Proc. IEEE
Stroud, Garimella & Sunwoo, On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in SoC Devices, Proc. ISCA International Conf. on Computers & Their Applications, 2005
Garimella & Stroud, A System for Automated Built-In Self-Test of
Embedded Memory Cores in System-on-Chip, Proc. IEEE
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella & Sunwoo, Built-In
Self-Test Configurations for Atmel FPGAs Using Macro Generation Language,
Proc. IEEE
Brooks Garrison, Analysis and Improvements of Virtex-4 Block RAM Built-In Self-Testand Introduction of Virtex-5 Block RAM Built-In Self-Test, AU MSEE thesis, 2009
currently working at Radiance Technologies in sunny
Dailey, Garrison, Pulukuri & Stroud, Built-In Self-Test of Embedded Memory Cores in Virtex-5 Field
Programmable Gate Arrays, Proc.
Garrison, Milton & Stroud, Built-In Self-Test of Embedded Memory Resources in Virtex-4 FPGAs, Proc. ISCA International Conf. on Computers and Their Applications, 2009
Jonathan Harris, Built-In Self-Test of Embedded Programmable Logic Cores in System-on-Chip Implementations, AU MSEE thesis, 2004
currently working at RF Micro Devices in sunny NC
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella & Sunwoo, Built-In
Self-Test Configurations for Atmel FPGAs Using Macro Generation Language,
Proc. IEEE
Lee Lerner, Built-In Self-Test of Input/Output Tiles in Field Programmable Gate Arrays, AU MSEE thesis, 2007
currently working at Luna Innovations in usually sunny VA
Dutton, Lerner, Vemula & Stroud, On System-Level Use of BIST for Programmable Input/Output Buffers in FPGAs, Proc. IEEE Southeast Regional Conf, 2010
Dutton, Lerner & Stroud, Built-In Self-Test of Programmable I/O
Cells in Virtex-4 FPGAS, Proc. IEEE
Lerner & Stroud, An Architecture for Fail-Silent Operation of FPGAs and Reconfigurable SoCs, Proc. International Conf. on Embedded Systems & Applications, 2006
Lerner, Vemula & Stroud, System-Level
BIST for Programmable I/O Buffers in FPGAs and SoCs,
Proc. IEEE
Alex Lusco, Evaluating the Digital Fault Coverage for a Mixed-Signal Built-In Self-Test, AU MSEE thesis, 2011
currently working at Google in mostly sunny GA
Lusco, Dailey & Stroud, Built-In
Self-Test for Multipliers in Cyclone II Field Programmable Gate Arrays,
Proc. IEEE
Lusco & Stroud, PSIM: A Processor Simultor for Basic Computer
Architecture and Operation Education, Proc. IEEE Southeast Regional Conf.,
2010
Daniel Milton, Built-In Self-Test of Configurable Memory Resources in Field Programmable Gate Arrays, AU MSEE thesis, 2007
currently working at Harris in sunny FL
Garrison, Milton & Stroud, Built-In Self-Test of Embedded Memory Resources in Virtex-4 FPGAs, Proc. ISCA International Conf. on Computers and Their Applications, 2009
Milton, Dhingra & Stroud, Embedded Processor Based BIST and Diagnosis of Logic and Memory Resources in FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2006
Dhingra, Milton & Stroud, BIST of Logic and Memory Resources in
Virtex-4 FPGAs, Proc. IEEE
Aditya Newalkar, Alternative Methods for Built-In Self-Test of Field Programmable Gate Arrays, AU MSEE thesis, 2005
currently working at GE in not-so-sunny MN
Dhingra, Garimella, Newalkar &
Stroud, Built-In Self-Test for Virtex and Spartan
II FPGAs Using Partial Reconfiguration, Proc. IEEE
Mary Pulukuri, Built-In Self-Test of Digital Signal
Processor Cores in Virtex-4 and Virtex-5 Field Programmable Gate Arrays,
AU MSEE thesis, 2010
currently working, doing a great job, and enjoying life in some
sunny place
Dailey, Garrison, Pulukuri & Stroud, Built-In Self-Test of Embedded Memory Cores
in Virtex-5 Field Programmable Gate Arrays, Proc.
Pulukuri & Stroud, On Built-In Self-Test of Adders, J. Electronic Testing: Theory & Applications, Vol. 25, No. 6, 2009
Pulukuri & Stroud, Built-In
Self-Test of Digital Signal Processors in Virtex-4 FPGAs, Proc. IEEE
Pulukuri, Starr & Stroud, On Built-In Self-Test of Multipliers, Proc. IEEE Southeast Regional Conf, 2010
Jie Qin, Slective
Spectrum Analysis and Numerically Controlled Oscillator in Mixed Signal
Built-In Self-Test, AU PhD dissertation, 2010, Auburn University Outstanding PhD Student for 2009-10, Electrical
& Computer Engineering Outstanding International Graduate Student for
2008-09, currently working for Lattice Semiconductor in sometimes sunny PA
Qin,
Qin, Stroud & Dai, FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems, IEEE Trans. on Industrial Electronics, 2007
Starr, Qin, Dutton, Stroud, Dai & Nelson, Automated Generation of BIST and Measurement Circuitry for Mixed-Signal Circuits and Systems, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009
Qin, Stroud & Dai, Test Time
of Multiplier/Accumulator Based Output Response Analyzer in Built-In Analog
Functional Testing, Proc. IEEE
Qin, Stroud & Dai, Noise Figure Measurement Using Mixed-Signal BIST, Proc. IEEE International Symp. on Circuits and Systems, 2007
Qin, Stroud & Dai, Phase
Delay Measurement and Calibration in Built-In Analog Functional Testing,
Proc. IEEE
Qin, Stroud & Dai, Phase Delay in MAC-based Analog Functional Testing in Mixed-Signal Systems, Proc. IEEE North Atlantic Test Workshop, 2006
Tacey, Lusco, Da Cunha &
Qin, Weighted Bridging Fault Coverage Using Capacitance Extraction,
Proc.
George Starr, Built-In Self-Test for Analysis of
Mixed-Signal Systems, AU MSEE thesis, 2010
currently working for CREE in
sunny NC
Qin,
Starr, Qin, Dutton, Stroud, Dai & Nelson, Automated Generation of BIST and Measurement Circuitry for Mixed-Signal Circuits and Systems, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009
Starr, Wersinger, Chapman, Riggs, Nelson, Klingelhoeffer & Stroud, Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies, Proc. International Conf. on Embedded Systems and Applications, 2009
Pulukuri, Starr & Stroud, On Built-In Self-Test of Multipliers, Proc. IEEE Southeast Regional Conf, 2010
John Sunwoo,
Built-In Self-Test of Programmable
Resources in Microcontroller Based System-on-Chips, AU MSEE thesis,
2005
currently pursuing a PhD at USC in sunny CA
Dutton, Ali, Stroud & Sunwoo, Embedded Fault and SEU Injection in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Sunwoo & Stroud, Built-In Self-Test of Configurable Cores in SoCs Using Embedded Processor Dynamic Reconfiguration, Proc. International SoC Design Conf., 2005
Sunwoo,
Garimella & Stroud, On Embedded Processor
Reconfiguration of Logic BIST for FPGA Cores in SoCs,
Proc. IEEE
Stroud, Garimella & Sunwoo, On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in SoC Devices, Proc. ISCA International Conf. on Computers and Their Applications, 2005
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella
& Sunwoo, Built-In Self-Test
Configurations for Atmel FPGAs Using Macro Generation Language, Proc. IEEE
Sudheer Vemula, Built-In Self-Test for Input/Output Cells in Field Programmable Gate Arrays, AU MSEE thesis, 2006
currently working at Altera
in sunny CA
Dutton, Lerner, Vemula & Stroud, On System-Level Use of BIST for Programmable Input/Output Buffers in FPGAs, Proc. IEEE Southeast Regional Conf, 2010
Vemula
& Stroud, Built-In Self-Test for
Programmable I/O Buffers in FPGAs and SoCs, Proc.
IEEE
Lerner, Vemula & Stroud, System-Level
BIST for Programmable I/O Buffers in FPGAs and SoCs,
Proc. IEEE
Vemula & Stroud, Built-In
Self-Test of I/O Buffers in Atmel FPGAs, Proc. IEEE
Jia Yao, Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs, AU MSEE thesis, 2009
currently pursuing a PhD at
sunny Auburn Univ.
Undergraduate Honors Students:
Mustafa Ali (4/06-7/07
Virtex-4 BIST), Emulated Fault Injection for Built-In Self-Test of Virtex-4 FPGAS
using Boundary Scan, AU Undergraduate Honors
Thesis, 2007
Dutton, Ali, Stroud & Sunwoo, Embedded Fault and SEU Injection in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Alex Lusco (8/09-5/10 Mixed-Signal BIST), PSIM: A Processor Simulator for Basic Compuer Architecture and Operation Education, AU Undergraduate Honors Thesis, 2010
Lusco & Stroud, PSIM: A Processor Simultor for Basic Computer
Architecture and Operation Education, Proc. IEEE Southeast Regional Conf.,
2010
Undergraduate Students:
Sidney Alamy (1/07-5/07 Virtex-4 RAM BIST)
Ken Andrews (8/07-12/07 Virtex-4 PPC BIST)
David Baumann (5/07-7/07
Virtex-4 BIST)
Jarred Beck (1/10-4/10 AdvanTest machine)
Braden Blackwell (5/04-8/04 SoC BIST demo board)
Bryan Blandin (1/10-4/10
AdvanTest machine)
Mallory Carson (1/11-9/11
Spartan-6 CLB BIST)
Tyler Crumpton
(5/11-9/11 Spartan-6 RAM BIST)
Charles Gilbert (1/07-5/07 Virtex-4 RAM BIST)
Lauren Goff (8/07-12/07 Virtex-4 PPC BIST)
Nick Hall (8/04-12/04 SoC BIST demo board)
Mitchell Hatley (5/04-12/04 SoC BIST demo board)
Myers Hawkins (1/10-4/10
mixed-sginal BIST)
Chris Hodges (5/06-8/06 Virtex-4 BIST)
Eric Ingram (9/09-4/10
multiplier BIST)
Patrick Kerrigan (9/06-11/06 Virtex-4 BIST)
Noah Larsen (5/07-7/07 Virtex-4 BIST)
James ONeill (1/11-4/11
BIST for FPGAs)
Clint Patterson (9/07-11/07
Virtex-4 BIST)
Alexander Pfeiffenberger (5/10-8/10 FPGA BIST)
Jared Phillips (5/04-12/04 - FPGA GUI)
Rebecca Skipper (5/04-12/04 - SoC BIST demo board)
Bill Tomas (1/10-4/10 multiplier BIST)
Andrew Tomlinson (1/10-4/10 AdvanTest machine)
Navit Yahdav (1/10-8/10 FPGA BIST)
Previous
BIST Dudes & Dudettes from
Graduate
Students:
Hazem Alassaly, Evaluation of Mixed-Signal Built-In Self-Test Via Physical Fault Insertion in a Continuous Time State Variable Filter, UNCC MSEE project, 2003
currently a PhD student at UNC-Charlotte
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Atia Islam, Parameterized VHDL Design of the Output Response Analyzer and Test Controller for Built-In Self-Test of Mixed-Signal Systems, UNCC MSEE thesis, 2003
currently a PhD student at Arizona State Univ.
Stroud, Morton & Islam, An Automated BIST Approach for Mixed-Signal Systems, Proc. IEEE
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Matt Lashinsky, On-Line Built-In Self-Test of Field Programmable Gate Array Interconnect Resources, UNCC MSEE thesis, 2001 (Finalist for Cameron Applied Research Award, 2001)
currently working at Lexmark in KY
Stroud, Nall, Lashinsky & Abramovici, BIST-Based Diagnosis of FPGA Interconnect, Proc. IEEE International Test Conf,, 2002
Stroud, Lashinsky, Nall, Emmert & Abramovici, On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs, Proc. IEEE International On-Line Testing Symp, 2001
Jason Morton, A Parameterized VHDL Model for a Test Pattern Generator for Built-In Self-Test of Analog and Mixed-Signal Circuits, UNCC MSEE thesis, 2003
current position unknown
Stroud, Morton & Islam, An Automated
BIST Approach for Mixed-Signal Systems, Proc. IEEE
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Jeremy Nall, On-Line Diagnosis of Field Programmable Gate Array Interconnect Resources, UNCC MSEE thesis, 2002 (Finalist for Cameron Applied Research Award, 2002)
currently working at Intel in AZ
Stroud, Nall, Lashinsky & Abramovici, BIST-Based Diagnosis of FPGA Interconnect, Proc. IEEE International Test Conf,, 2002
Stroud, Nall, Taylor, Ford & Charnley, A System for Automated Generation of Built-In Self-Test for FPGAs, Proc. International Conf. on System Engineering, 2002
Stroud, Lashinsky, Nall, Emmert & Abramovici, On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs, Proc. IEEE International On-Line Testing Symp, 2001
Undergraduate
Students:
Mark Ford, (5/02-12/02 - Mixed-Signal BIST)
Stroud, Nall, Taylor, Ford & Charnley, A System for Automated Generation of Built-In Self-Test for FPGAs, Proc. International Conf. on System Engineering, 2002
Stefan Ivanoff, (5/02-12/02 - Mixed-Signal BIST)
Chris Mays, (5/01-8/02 - iDDT Testing)
Thomas Slaughter, (6/00-5/03 - BIST for FPGAs)
Stroud, Leach & Slaughter, BIST for Xilinx 4000 and Spartan Series FPGAs: a Case Study, Proc. IEEE International Test Conf., 2003
Slaughter & Stroud, Fault Injection Emulation in Field Programmable Analog Arrays, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Slaughter, Stroud, Emmert & Skaggs, Fault Injection Emulation for Field Programmable Gate Arrays, Proc. ITCOM, 2001
Mario Tooley, (5/02-8/02 - FPGA Logic BIST Timing Analysis)
Previous
BIST Dudes & Dudettes from
Graduate
Students:
Jamie Bailey, Manufacturing Test Development for Complex Programmable Logic Devices, UK MSEE thesis, 2001
currently working at Lexmark in KY
Stroud, Bailey & Emmert, A New Method for Testing Re-programmable PLAs, J. Electronic Testing: Theory & Applications, Vol. 16, No. 6, 2000
Bailey & Stroud, Embedded Logic Analyzer for On-Line System Analysis, Proc. International Conf. on Information Systems Analysis and Synthesis, 2002
Stroud, Bailey, Emmert, Nickolic, & Chhor, Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development, Proc. IEEE International Test Conf., 2000
Stroud, Emmert, & Bailey, A New Bridging Fault Model for More Accurate Fault Behavior, Proc. IEEE Automatic Test Conf., 2000
Bailey, Stroud, Chhor, Lau & Orso, A Method for Testing Partially Programmable Logic Arrays in CPLDs, Proc. IEEE Automatic Test Conf., 2000
Ping Chen, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, UK MSEE thesis, 1995
current position unknown
Stroud, Konala, Chen, & Abramovici, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, Proc. IEEE VLSI Test Symp., 1996
Stroud, Chen, Konala & Abramovici, Evaluation of FPGA Resources for BIST of Programmable Logic Blocks, Proc. ACM International Symp. on FPGAs, 1996
Abramovici, Chen & Stroud, Finally, A Free Lunch: BIST (for FPGAs) Without Overhead!, Proc. AT&T Conf. on Electronic Testing, 1995
Chandan Das, Multiple Fanout Static Routing Network for Field Programmable Printed Circuit Boards, UK MSEE thesis, 1995
currently working at Intel in AZ
Das & Stroud, A Multiple Fan-out Static Routing Scheme for Field Programmable Printed Circuit Boards, Proc. IEEE International Application Specific Integrated Circuits Conf., 1995
Ming Ding, Merging Concurrent Fault Detection Circuits with Off-Line/On-Line Built-In Self-Test, UK MSEE thesis, 1997
currently working at Lattice in CA
Stroud, Ding, Seshadri, Kim,
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Karri, Wu, Stroud, & Ding, Parameterized VHDL Library for On-Line Testing, Proc. Lucent Technologies Electronic Testing Conf., 1998
Travis Ferry, Recovery of Faulty Processing Elements in Array Processors Using Threshold Functions, UK MSEE thesis, 1996
current position unknown
Stroud, Emmert, Taylor & Ferry, Recovering Faulty Processing Elements to Enhance Reliability and Lifecycle in VLSI Processor Arrays, Proc. IEEE Automatic Test Conf., 2001 (Best Paper Award)
Gretchen Gibson, Boundary Scan Access to Built-In Self-Test for Field Programmable Gate Arrays, UK MSEE thesis, 1998
currently working at Lexmark in KY
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Gibson, Gray & Stroud, Boundary Scan Access to BIST for Field Programmable Gate Arrays, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Carter Hamilton, On-Line Testing and Reconfiguration of Field Programmable Gate Arrays, UK MSEE thesis, 2000
currently working at Xilinx in CA
Abramovici, Stroud, Hamilton, Wijesuriya & Verma, On-Line Testing and Diagnosis of FPGAs with Roving STARs, Proc. IEEE International On-Line Testing Symp., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International Test Conf., 1998
Abramovici,
Stroud,
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International On-Line Testing Symp., 1998
Ping He, Synthesis of Modified Circular Built-In Self-Test, UK MSEE thesis, 1996
current position unknown
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Stroud, He, & Damarla, Register Size vs. Fault Coverage in Modified Circular Built-In Self-Test, Proc. IEEE Automatic Test Conf., 1996
Piyumani Karunaratna, Digital Components for Built-In Self-Test of Analog Circuits, UK MSEE thesis, 1998
current position unknown
Stroud, Karunaratna, & Bradley, Digital Components for Built-In Self-Test of Analog Circuits, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Srinivasa Konala, Implementation of Built-In Self-Test Configurations for Field Programmable Gate Arrays, UK MSEE thesis, 1996
currently working at Intel in AZ
Stroud, Lee, Konala & Abramovici, Using ILA Testing for BIST in FPGAs, Proc. IEEE International Test Conf., 1996
Stroud, Lee, Konala & Abramovici, Selecting Built-In Self-Test Configurations for Field Programmable Gate Arrays, Proc. IEEE Automatic Test Conf., 1996
Stroud, Konala, Chen & Abramovici, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, Proc. IEEE VLSI Test Symp., 1996
Stroud, Chen, Konala & Abramovici, Evaluation of FPGA Resources for BIST of Programmable Logic Blocks, Proc. ACM International Symp. on FPGAs, 1996
Eric Lee, Built-In Self-Test and Diagnostics for Field Programmable Gate Arrays, UK MSEE thesis, 1997
currently working at Lattice in PA
Abramovici, Lee, Stroud & Underwood, Self-Test for FPGAs and CPLDs Requires No Overhead, Electronic Design, Nov., 1997
Stroud, Lee, & Abramovici, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International Test Conf., 1997
Abramovici, Lee, & Stroud, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International On-Line Testing Symp.1997
Stroud, Lee, Konala & Abramovici, Using ILA Testing for BIST in FPGAs, Proc. IEEE International Test Conf., 1996
Stroud, Lee, Konala & Abramovici, Selecting Built-In Self-Test Configurations for Field Programmable Gate Arrays, Proc. IEEE Automatic Test Conf., 1996
Wai Khuan Long, Using On-Line Functions for Off-Line Testing in Digital Systems, UK MSEE thesis, 1998
current position unknown
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Kristi Maggard, Evaluation of Mixed-Signal Built-In Self-Test for Analog Circuits, UK MSEE thesis, 1999
currently working at Lexmark in KY
Maggard & Stroud, Built-In Self-Test for Analog Circuits in Mixed-Signal Systems, Proc. IEEE Southeast Regional Conf., 1999
Kondagunturi, Bradley, Magard & Stroud, Benchmark Circuits for Analog and Mixed-Signal Testing, Proc. IEEE Southeast Regional Conf., 1999
Andrew Russ, Non-Intrusive Built-In Self-Test for Field Programmable Gate Array and Multi-Chip Module Applications, UK MSEE thesis, 1995
currently working at Lexmark in KY
Russ & Stroud, Non-Intrusive Built-In Self-Test for FPGA and MCM Applications, Proc. IEEE Automatic Test Conf., 1995
Kripa Sankaranarayanan, Field Programmable Gate Array Based Implementation of Monobit Fast Fourier Transform Receiver Design, UK MSEE thesis, 2001
currently working at Intel in OR
Sankaranarayanan & Stroud, Built-In
Self-Test for a Monobit Fast Fourier Transform
Receiver, Proc. IEEE
Sowmya Seshadri, Modeling and Synthesis of Concurrent Fault Detection Circuits, UK MSEE thesis, 1997
currently working at Synopsys in CA
Stroud, Ding, Seshadri, Kim,
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Brandon Skaggs, On-Line Built-In Self-Test and Diagnosis of Field Programmable Gate Array Logic Blocks, UK MSEE thesis, 2000
currently working at Lexmark in KY
Abramovici, Stroud, Skaggs, & Emmert, Improving BIST-Based Diagnosis for Roving STARs, Proc. IEEE International On-Line Testing Symp, 2000
Emmert, Stroud, Skaggs, & Abramovici, Dynamic Fault Tolerance in FGPAs via Partial Reconfiguration, Proc. Field Programmable Custom Computing Machines Conf., 2000
Slaughter, Stroud, Emmert & Skaggs, Fault Injection Emulation for Field Programmable Gate Arrays, Proc. ITCOM, 2001
Malissa Sullivan, Replacement and Ordering of Circular Built-In Self-Test Flip-Flops, UK MSEE thesis, 1995
currently working at DataBeam in KY
Sullivan & Stroud, Reducing the Cost of Circular Built-In Self-Test by Selective Flip-Flop Replacement, Proc. IEEE Automatic Test Conf., 1995
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Joe Tannehill, Jr., Built-In Self-Test for Majority Voting Fault-Tolerant Digital Circuits, UK MSEE thesis, 1994
current position unknown
Stroud & Tannehill, Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits, Proc. IEEE VLSI Test Symp., 1998
Stan Tungate, Limit Cycling in Circular Built-In Self-Test, UK MSEE thesis, 1996
currently working at Lexmark in KY
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Damarla, Stroud, Tungate, Keyes, & Michael, Improving the Effectiveness of Circular BIST, Tech. Digest Government Microelectronics Applications Conf, 1996
Nick Vocke, Routing Algorithms for Complex Programmable Logic Devices, UK MSEE thesis, 2000 (co-advisor: Dr. R. Heath)
currently working at Intel in AZ
Heath, Vocke, Stroud & Emmert, Routing Algorithms for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Automatic Test Conf. 2001
Vocke, Stroud, Heath, Chhor, & Orso, Computer Aided Routing for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Southeast Regional Conf., 2000
Sajitha Wijesuriya, Built-In Self-Test for Programmable Interconnect in Field Programmable Gate Arrays, UK MSEE thesis, 1999
currently working at Lattice in PA
Abramovici, Stroud, Hamilton, Wijesuriya & Verma, On-Line Testing and Diagnosis of FPGAs with Roving STARs, Proc. IEEE International On-Line Testing Symp., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International Test Conf., 1998
Abramovici,
Stroud,
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International On-Line Testing Symp., 1998
Yingchang Yang, Maximizing the Effectiveness of On-Line Testing Functions, UK MSEE thesis, 1998
current position unknown
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Undergraduate
Students:
Matt Carter, (5/99-12/99 - On-Line BIST of FPGA Interconnect)
Angela Christopher, (8/95-12/95 - Hardware for Testing VLSI Devices Fabricated Through MOSIS)
Cory Davis, (1/00-5/00 - CPLD Based Embedded Logic Analyzer)
Gwyn Everly, (1/98-5/98 - VHDL Modeling for On-Line Test)
Lisa Gray, (5/96-5/97 - Boundary Scan Access to FPGAs)
Gibson, Gray & Stroud, Boundary Scan Access to BIST for Field Programmable Gate Arrays, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Robert Hallquist, (1/95-5/95 - BIST Configurations for FPGA Logic Blocks)
Brandon Lewis, (8/98-12/98 - Prototype Unit for BIST for Analog Circuits)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
Sheac Yee Lim, (1/99-5/99 Prototype Unit for BIST for Analog Circuits)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
Bob Puckett, (8/97-12/97 - Mixed-Signal BIST Digital-to-Analog Converter)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
James Roller, (8/99-5/00 - On-Line BIST of FPGA Interconnect)
Jeff Spitler, (1/00-5/00 - CPLD Based Embedded Logic Analyzer)
Shannon Spencer, (5/95-8/95 - Software for Testing VLSI Devices Fabricated Through MOSIS)