Previous graduates from the:
Graduate
Students:
Bobby Dixon, Built-In Self-Test of the Programmable
Interconnect in Field Programmable Gate Arrays, AU MSEE thesis, 2008
currently working for the
Navy in sunny
Dixon & Stroud, Analysis
and Evaluation of Routing BIST Approaches for FPGAs, Proc. IEEE
Sachin Dinghra, Built-In Self-Test of Logic Resources in
Field Programmable Gate Arrays Using Partial Reconfiguration, AU MSEE
thesis, 2006
currently working at Altera
in sunny CA
Milton, Dhingra & Stroud, Embedded Processor Based BIST and Diagnosis of Logic and Memory Resources in FPGAs,” Proc. International Conf. on Embedded Systems and Applications, 2006
Dhingra, Milton & Stroud, BIST
of Logic and Memory Resources in Virtex-4 FPGAs, Proc. IEEE
Dhingra, Garimella, Newalkar & Stroud, Built-In Self-Test
for Virtex and Spartan II FPGAs Using Partial Reconfiguration, Proc. IEEE
Srinivas Garimella, Built-In Self-Test of Embedded Memory
Cores in System-on-Chip Implementations, AU MSEE thesis, 2005, Auburn University Outstanding MS Student for 2004-05
currently working at Altera
in sunny CA
Stroud & Garimella, Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs, Proc. International Conf. on Embedded Systems and Applications, 2005
Dhingra, Garimella, Newalkar & Stroud, Built-In Self-Test for Virtex and Spartan II FPGAs Using Partial
Reconfiguration, Proc. IEEE
Sunwoo, Garimella & Stroud, On
Embedded Processor Reconfiguration of Logic BIST for FPGA Cores in SoCs,
Proc. IEEE
Stroud, Garimella & Sunwoo, On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in SoC Devices, Proc. ISCA International Conf. on Computers & Their Applications, 2005
Garimella & Stroud, A
System for Automated Built-In Self-Test of Embedded Memory Cores in
System-on-Chip, Proc. IEEE
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella & Sunwoo, Built-In Self-Test Configurations for Atmel
FPGAs Using Macro Generation Language, Proc. IEEE
Brooks Garrison, Analysis and Improvements of Virtex-4 Block RAM Built-In Self-Testand Introduction of Virtex-5 Block RAM Built-In Self-Test, AU MSEE thesis, 2009
currently working at Radiance
Technologies in Huntsville AL
Garrison, Milton & Stroud, Built-In Self-Test of Embedded Memory Resources in Virtex-4 FPGAs,” Proc. ISCA International Conf. on Computers and Their Applications, 2009
Jonathan Harris, Built-In Self-Test of Embedded Programmable Logic Cores in System-on-Chip Implementations, AU MSEE thesis, 2004
currently working at RF Micro Devices back near his home in NC
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella
& Sunwoo, Built-In Self-Test Configurations for Atmel FPGAs Using Macro
Generation Language, Proc. IEEE
Lee Lerner, Built-In Self-Test of Input/Output Tiles in Field Programmable Gate Arrays, AU MSEE thesis, 2007
currently working at Luna Innovations in VA
Dutton, Lerner & Stroud, Built-In Self-Test of Programmable I/O
Cells in Virtex-4 FPGAS, Proc. IEEE
Lerner & Stroud, An Architecture for Fail-Silent Operation of FPGAs and Reconfigurable SoCs, Proc. International Conf. on Embedded Systems & Applications, 2006
Lerner, Vemula & Stroud, System-Level
BIST for Programmable I/O Buffers in FPGAs and SoCs, Proc. IEEE
Daniel Milton, Built-In Self-Test of Configurable Memory Resources in Field Programmable Gate Arrays, AU MSEE thesis, 2007
currently working at Harris
in sunny
Garrison, Milton & Stroud, Built-In Self-Test of Embedded Memory Resources in Virtex-4 FPGAs,” Proc. ISCA International Conf. on Computers and Their Applications, 2009
Milton, Dhingra & Stroud, Embedded Processor Based BIST and Diagnosis of Logic and Memory Resources in FPGAs,” Proc. International Conf. on Embedded Systems and Applications, 2006
Dhingra, Milton & Stroud, BIST of
Logic and Memory Resources in Virtex-4 FPGAs, Proc. IEEE
Aditya Newalkar, Alternative Methods for Built-In Self-Test of Field Programmable Gate Arrays, AU MSEE thesis, 2005
currently working at GE in not-so-sunny MN
Dhingra, Garimella, Newalkar &
Stroud, Built-In Self-Test for Virtex and Spartan II FPGAs Using Partial
Reconfiguration, Proc. IEEE
John Sunwoo, Built-In Self-Test of Programmable
Resources in Microcontroller Based System-on-Chips, AU MSEE thesis,
2005
currently working at
Electronics and Telecommunications Research Institute in
Dutton, Ali, Stroud & Sunwoo, Embedded Fault and SEU Injection in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Sunwoo & Stroud, Built-In Self-Test of Configurable Cores in SoCs Using Embedded Processor Dynamic Reconfiguration, Proc. International SoC Design Conf., 2005
Sunwoo, Garimella &
Stroud, On Embedded Processor Reconfiguration of Logic BIST for FPGA Cores
in SoCs, Proc. IEEE
Stroud, Garimella & Sunwoo, On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in SoC Devices, Proc. ISCA International Conf. on Computers and Their Applications, 2005
Stroud, Sunwoo, Garimella & Harris, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004
Stroud, Harris, Garimella & Sunwoo,
Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation
Language, Proc. IEEE
Sudheer Vemula, Built-In Self-Test for Input/Output Cells in Field Programmable Gate Arrays, AU MSEE thesis, 2006
currently working at Altera
in sunny CA
Vemula
& Stroud, Built-In Self-Test for
Programmable I/O Buffers in FPGAs and SoCs, Proc. IEEE
Lerner, Vemula & Stroud, System-Level
BIST for Programmable I/O Buffers in FPGAs and SoCs, Proc. IEEE
Vemula & Stroud, Built-In
Self-Test of I/O Buffers in Atmel FPGAs, Proc. IEEE
Jia Yao, Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs, AU MSEE thesis, 2009
currently pursuing PhD at
Undergraduate Students:
Neil Da Cunha (6/09-8/09 – Virtex-4
& Virtex-5 BIST)
Mustafa Ali (4/06-7/07
– Virtex-4 BIST), Emulated Fault Injection for Built-In Self-Test of Virtex-4 FPGAS
using Boundary Scan, AU Undergraduate Honors
Thesis, 2007
Dutton, Ali, Stroud & Sunwoo, Embedded Fault and SEU Injection in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009
Sidney Alamy (1/07-5/07 – Virtex-4 RAM BIST)
Ken Andrews (8/07-12/07 – Virtex-4 PPC BIST)
David Baumann (5/07-7/07
– Virtex-4 BIST)
Braden Blackwell (5/04-8/04 – SoC BIST demo board)
Charles Gilbert (1/07-5/07 – Virtex-4 RAM BIST)
Lauren Goff (8/07-12/07 – Virtex-4 PPC BIST)
Nick Hall (8/04-12/04 – SoC BIST demo board)
Mitchell Hatley (5/04-12/04 – SoC BIST demo board)
Chris Hodges (5/06-8/06 – Virtex-4 BIST)
Patrick Kerrigan (9/06-11/06 – Virtex-4 BIST)
Noah Larsen (5/07-7/07
– Virtex-4 BIST)
Clint Patterson (9/07-11/07
– Virtex-4 BIST)
Jared Phillips (5/04-12/04 - FPGA GUI)
Rebecca Skipper (5/04-12/04 - SoC BIST demo board)
Previous
BIST Dudes & Dudettes from University of North Carolina at Charlotte
Graduate Students:
Hazem Alassaly, Evaluation
of Mixed-Signal Built-In Self-Test Via Physical Fault Insertion in a Continuous
Time State Variable Filter, UNCC MSEE project, 2003
currently a PhD student at UNC-Charlotte
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Atia Islam, Parameterized VHDL Design of the Output Response Analyzer and Test Controller for Built-In Self-Test of Mixed-Signal Systems, UNCC MSEE thesis, 2003
currently a PhD student at Arizona State Univ.
Stroud, Morton & Islam, An Automated BIST Approach for
Mixed-Signal Systems, Proc. IEEE
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Matt Lashinsky, On-Line Built-In Self-Test of Field Programmable Gate Array Interconnect Resources, UNCC MSEE thesis, 2001 (Finalist for Cameron Applied Research Award, 2001)
currently working at Lexmark in KY
Stroud, Nall, Lashinsky & Abramovici, BIST-Based Diagnosis of FPGA Interconnect, Proc. IEEE International Test Conf,, 2002
Stroud, Lashinsky, Nall, Emmert & Abramovici, On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs, Proc. IEEE International On-Line Testing Symp, 2001
Jason Morton, A Parameterized VHDL Model for a Test Pattern Generator for Built-In Self-Test of Analog and Mixed-Signal Circuits, UNCC MSEE thesis, 2003
current position unknown
Stroud, Morton & Islam, An Automated BIST Approach for Mixed-Signal
Systems, Proc. IEEE
Stroud, Morton, Islam & Alassaly, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Jeremy Nall, On-Line Diagnosis of Field Programmable Gate Array Interconnect Resources, UNCC MSEE thesis, 2002 (Finalist for Cameron Applied Research Award, 2002)
currently working at Intel in AZ
Stroud, Nall, Lashinsky & Abramovici, BIST-Based Diagnosis of FPGA Interconnect, Proc. IEEE International Test Conf,, 2002
Stroud, Nall, Taylor, Ford & Charnley, A System for Automated Generation of Built-In Self-Test for FPGAs, Proc. International Conf. on System Engineering, 2002
Stroud, Lashinsky, Nall, Emmert & Abramovici, On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs, Proc. IEEE International On-Line Testing Symp, 2001
Undergraduate
Students:
Mark Ford, (5/02-12/02 - Mixed-Signal BIST)
Stroud, Nall, Taylor, Ford & Charnley, A System for Automated Generation of Built-In Self-Test for FPGAs, Proc. International Conf. on System Engineering, 2002
Stefan Ivanoff, (5/02-12/02 - Mixed-Signal BIST)
Chris Mays, (5/01-8/02 - iDDT Testing)
Thomas Slaughter, (6/00-5/03 - BIST for FPGAs)
Stroud, Leach & Slaughter, BIST for Xilinx 4000 and Spartan Series FPGAs: a Case Study, Proc. IEEE International Test Conf., 2003
Slaughter & Stroud, Fault Injection Emulation in Field Programmable Analog Arrays, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003
Slaughter, Stroud, Emmert & Skaggs, Fault Injection Emulation for Field Programmable Gate Arrays, Proc. ITCOM, 2001
Mario Tooley, (5/02-8/02 - FPGA Logic BIST Timing Analysis)
Previous
BIST Dudes & Dudettes from
Graduate
Students:
Jamie Bailey, Manufacturing Test Development for Complex Programmable Logic Devices, UK MSEE thesis, 2001
currently working at Lexmark in KY
Stroud, Bailey & Emmert, A New Method for Testing Re-programmable PLAs, J. Electronic Testing: Theory & Applications, Vol. 16, No. 6, 2000
Bailey & Stroud, Embedded Logic Analyzer for On-Line System Analysis, Proc. International Conf. on Information Systems Analysis and Synthesis, 2002 (received Best Paper Award)
Stroud, Bailey, Emmert, Nickolic, & Chhor, Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development, Proc. IEEE International Test Conf., 2000
Stroud, Emmert, & Bailey, A New Bridging Fault Model for More Accurate Fault Behavior, Proc. IEEE Automatic Test Conf., 2000
Bailey, Stroud, Chhor, Lau & Orso, A Method for Testing Partially Programmable Logic Arrays in CPLDs, Proc. IEEE Automatic Test Conf., 2000
Ping Chen, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, UK MSEE thesis, 1995
current position unknown
Stroud, Konala, Chen, & Abramovici, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, Proc. IEEE VLSI Test Symp., 1996
Stroud, Chen, Konala & Abramovici, Evaluation of FPGA Resources for BIST of Programmable Logic Blocks, Proc. ACM International Symp. on FPGAs, 1996
Abramovici, Chen & Stroud, Finally, A Free Lunch: BIST (for FPGAs) Without Overhead!, Proc. AT&T Conf. on Electronic Testing, 1995
Chandan Das, Multiple Fanout Static Routing Network for Field Programmable Printed Circuit Boards, UK MSEE thesis, 1995
currently working at Intel in AZ
Das & Stroud, A Multiple Fan-out Static Routing Scheme for Field Programmable Printed Circuit Boards, Proc. IEEE International Application Specific Integrated Circuits Conf., 1995
Ming Ding, Merging Concurrent Fault Detection Circuits with Off-Line/On-Line Built-In Self-Test, UK MSEE thesis, 1997
currently working at Lattice in CA
Stroud, Ding, Seshadri, Kim,
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Karri, Wu, Stroud, & Ding, Parameterized VHDL Library for On-Line Testing, Proc. Lucent Technologies Electronic Testing Conf., 1998
Travis Ferry, Recovery of Faulty Processing Elements in Array Processors Using Threshold Functions, UK MSEE thesis, 1996
current position unknown
Stroud, Emmert, Taylor & Ferry, Recovering Faulty Processing Elements to Enhance Reliability and Lifecycle in VLSI Processor Arrays, Proc. IEEE Automatic Test Conf., 2001
Gretchen Gibson, Boundary Scan Access to Built-In Self-Test for Field Programmable Gate Arrays, UK MSEE thesis, 1998
currently working at Lexmark in KY
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Gibson, Gray & Stroud, Boundary Scan Access to BIST for Field Programmable Gate Arrays, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Carter Hamilton, On-Line Testing and Reconfiguration of Field Programmable Gate Arrays, UK MSEE thesis, 2000
currently working at Xilinx in CA
Abramovici, Stroud, Hamilton, Wijesuriya & Verma, On-Line Testing and Diagnosis of FPGAs with Roving STARs, Proc. IEEE International On-Line Testing Symp., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International Test Conf., 1998
Abramovici, Stroud,
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International On-Line Testing Symp., 1998
Ping He, Synthesis of Modified Circular Built-In Self-Test, UK MSEE thesis, 1996
current position unknown
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Stroud, He, & Damarla, Register Size vs. Fault Coverage in Modified Circular Built-In Self-Test, Proc. IEEE Automatic Test Conf., 1996
Piyumani Karunaratna, Digital Components for Built-In Self-Test of Analog Circuits, UK MSEE thesis, 1998
current position unknown
Stroud, Karunaratna, & Bradley, Digital Components for Built-In Self-Test of Analog Circuits, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Srinivasa Konala, Implementation of Built-In Self-Test Configurations for Field Programmable Gate Arrays, UK MSEE thesis, 1996
currently working at Intel in AZ
Stroud, Lee, Konala & Abramovici, Using ILA Testing for BIST in FPGAs, Proc. IEEE International Test Conf., 1996
Stroud, Lee, Konala & Abramovici, Selecting Built-In Self-Test Configurations for Field Programmable Gate Arrays, Proc. IEEE Automatic Test Conf., 1996
Stroud, Konala, Chen & Abramovici, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, Proc. IEEE VLSI Test Symp., 1996
Stroud, Chen, Konala & Abramovici, Evaluation of FPGA Resources for BIST of Programmable Logic Blocks, Proc. ACM International Symp. on FPGAs, 1996
Eric Lee, Built-In Self-Test and Diagnostics for Field Programmable Gate Arrays, UK MSEE thesis, 1997
currently working at Lattice in PA
Abramovici, Lee, Stroud & Underwood, Self-Test for FPGAs and CPLDs Requires No Overhead, Electronic Design, Nov., 1997
Stroud, Lee, & Abramovici, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International Test Conf., 1997
Abramovici, Lee, & Stroud, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International On-Line Testing Symp.1997
Stroud, Lee, Konala & Abramovici, Using ILA Testing for BIST in FPGAs, Proc. IEEE International Test Conf., 1996
Stroud, Lee, Konala & Abramovici, Selecting Built-In Self-Test Configurations for Field Programmable Gate Arrays, Proc. IEEE Automatic Test Conf., 1996
Wai Khuan Long, Using On-Line Functions for Off-Line Testing in Digital Systems, UK MSEE thesis, 1998
current position unknown
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Kristi Maggard, Evaluation of Mixed-Signal Built-In Self-Test for Analog Circuits, UK MSEE thesis, 1999
currently working at Lexmark in KY
Maggard & Stroud, Built-In Self-Test for Analog Circuits in Mixed-Signal Systems, Proc. IEEE Southeast Regional Conf., 1999
Kondagunturi, Bradley, Magard & Stroud, Benchmark Circuits for Analog and Mixed-Signal Testing, Proc. IEEE Southeast Regional Conf., 1999
Andrew Russ, Non-Intrusive Built-In Self-Test for Field Programmable Gate Array and Multi-Chip Module Applications, UK MSEE thesis, 1995
currently working at Lexmark in KY
Russ & Stroud, Non-Intrusive Built-In Self-Test for FPGA and MCM Applications, Proc. IEEE Automatic Test Conf., 1995
Kripa Sankaranarayanan, Field Programmable Gate Array Based Implementation of Monobit Fast Fourier Transform Receiver Design, UK MSEE thesis, 2001
currently working at Intel in OR
Sankaranarayanan & Stroud, Built-In Self-Test for a Monobit
Fast Fourier Transform Receiver, Proc. IEEE
Sowmya Seshadri, Modeling and Synthesis of Concurrent Fault Detection Circuits, UK MSEE thesis, 1997
currently working at Synopsys in CA
Stroud, Ding, Seshadri, Kim,
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Brandon Skaggs, On-Line Built-In Self-Test and Diagnosis of Field Programmable Gate Array Logic Blocks, UK MSEE thesis, 2000
currently working at Lexmark in KY
Abramovici, Stroud, Skaggs, & Emmert, Improving BIST-Based Diagnosis for Roving STARs, Proc. IEEE International On-Line Testing Symp, 2000
Emmert, Stroud, Skaggs, & Abramovici, Dynamic Fault Tolerance in FGPAs via Partial Reconfiguration, Proc. Field Programmable Custom Computing Machines Conf., 2000
Slaughter, Stroud, Emmert & Skaggs, Fault Injection Emulation for Field Programmable Gate Arrays, Proc. ITCOM, 2001
Malissa Sullivan, Replacement and Ordering of Circular Built-In Self-Test Flip-Flops, UK MSEE thesis, 1995
currently working at DataBeam in KY
Sullivan & Stroud, Reducing the Cost of Circular Built-In Self-Test by Selective Flip-Flop Replacement, Proc. IEEE Automatic Test Conf., 1995
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Joe Tannehill, Jr., Built-In Self-Test for Majority Voting Fault-Tolerant Digital Circuits, UK MSEE thesis, 1994
current position unknown
Stroud & Tannehill, Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits, Proc. IEEE VLSI Test Symp., 1998
Stan Tungate, Limit Cycling in Circular Built-In Self-Test, UK MSEE thesis, 1996
currently working at Lexmark in KY
Tungate, He, Seshadri, Stroud, Sullivan, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996
Damarla, Stroud, Tungate, Keyes, & Michael, Improving the Effectiveness of Circular BIST, Tech. Digest Government Microelectronics Applications Conf, 1996
Nick Vocke, Routing Algorithms for Complex Programmable Logic Devices, UK MSEE thesis, 2000 (co-advisor: Dr. R. Heath)
currently working at Intel in AZ
Heath, Vocke, Stroud & Emmert, Routing Algorithms for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Automatic Test Conf. 2001
Vocke, Stroud, Heath, Chhor, & Orso, Computer Aided Routing for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Southeast Regional Conf., 2000
Glenn
currently working at Lexmark in KY
Westerman, Stroud, Heath, & Kumar, Delay Fault Analysis Using Discrete Event System Approach, Proc. IEEE Automatic Test Conf., 1998
Westerman, Kumar, Stroud, & Heath, Discrete Event System Approach for Delay Fault Analysis in Digital Circuits, Proc. American Control Conf., 1998
Westerman, Stroud, & Heath, Delay Fault Modeling and Testability Analysis Using Temporal Logic, Proc. IEEE Automatic Test Conf., 1997
Sajitha Wijesuriya, Built-In Self-Test for Programmable Interconnect in Field Programmable Gate Arrays, UK MSEE thesis, 1999
currently working at Lattice in PA
Abramovici, Stroud, Hamilton, Wijesuriya & Verma, On-Line Testing and Diagnosis of FPGAs with Roving STARs, Proc. IEEE International On-Line Testing Symp., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International Test Conf., 1998
Abramovici, Stroud,
Hamilton, Gibson, Wijesuriya & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999
Hamilton, Wijesuriya, Gibson & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999
Stroud, Wijesuriya, Hamilton & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International On-Line Testing Symp., 1998
Yingchang Yang, Maximizing the Effectiveness of On-Line Testing Functions, UK MSEE thesis, 1998
current position unknown
Stroud, Ding, Long, Yang, Karri, & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998
Undergraduate
Students:
Matt Carter, (5/99-12/99 - On-Line BIST of FPGA Interconnect)
Angela Christopher, (8/95-12/95 - Hardware for Testing VLSI Devices Fabricated Through MOSIS)
Cory Davis, (1/00-5/00 - CPLD Based Embedded Logic Analyzer)
Gwyn Everly, (1/98-5/98 - VHDL Modeling for On-Line Test)
Lisa Gray, (5/96-5/97 - Boundary Scan Access to FPGAs)
Gibson, Gray & Stroud, Boundary Scan Access to BIST for Field Programmable Gate Arrays, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997
Robert Hallquist, (1/95-5/95 - BIST Configurations for FPGA Logic Blocks)
Brandon Lewis, (8/98-12/98 - Prototype Unit for BIST for Analog Circuits)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
Sheac Yee Lim, (1/99-5/99 Prototype Unit for BIST for Analog Circuits)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
Bob Puckett, (8/97-12/97 - Mixed-Signal BIST Digital-to-Analog Converter)
Lewis, Lim, Puckett & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999
James Roller, (8/99-5/00 - On-Line BIST of FPGA Interconnect)
Jeff Spitler, (1/00-5/00 - CPLD Based Embedded Logic Analyzer)
Shannon Spencer, (5/95-8/95 - Software for Testing VLSI Devices Fabricated Through MOSIS)