ELEC 5250/6250 Computer-Aided Design of Digital Circuits
Next offering by C. Stroud
- uncertain at this point
General
Syllabus
Lecture notes for Dr. Nelson’s class on 9/25/07
Lecture Notes:
FPGA Notes:
Programmable
Logic
PLAs and
Programming Technologies
VLSI Notes:
History
of VLSI & Implementation Media
MOSFETs
MOS
Flip-Flops & Latches
Mixed-Signal
BIST Presentation
LFSRs
VHDL Notes:
HDLs in
the Design Process
VHDL
Entities, Architectures, and Processes
VHDL
Names, Signals, and Attributes
VHDL
Operators
VHDL
Constructs
VHDL
Combinational Logic Modeling
VHDL Sequential Logic Modeling
Testing Notes:
Overview of
Testing
Overview of Faults
Fault Modeling
and Detection
Assignments & Exercises from Fall 2004:
Assignment #1: Draw the gate-level and CMOS transistor-level circuit
diagrams for an AOI321 and an OAI321 labeling all I/O. Due at beginning of
class on Thursday 9/2.
Assignment
#2: Due at beginning of class
on Thursday 9/16.
Assignment
#3: Due beginning of class on Thursday 10/21.
Assignment #4: Due
beginning of class on Thursday 11/11.
Assignment
#5: Due beginning of class on Thursday 11/18. AUSIM manual
for the unix workstation version.
Assignment
#6: Due beginning of class on Thursday 12/7.
Specifications for Mixed-Signal Built-In Self-Test
Design Project - Revision 3
AUSIM L2.2 Manual
download
AUSIM L2.2 executable for PC
The download is a .zip file that contains the AUSIM manual, the PC executable,
and the example files that are discussed in the manual.
Reference Material:
XSA50 User's Manual
Xstend User's Manual
Xtools User's Manual
Xilinx Spartan II Data Sheet
Xilinx Virtex Data Sheet
Tutorial Documents for Mentor Graphics Tools