# 9 inputs ;
# 11 outputs ;
# 15 D-type flipflops ;
# 59 inverters ;
# 101 gates ( 44 ANDs + 18 NANDs + 9 ORs + 30 NORs 0 XORs 0 XNORs) ;
CKT: s344
IN: CK START B0 B1 B2 B3
A0 A1 A2 A3 
OUT: P4 P5 P6 P7 P0
P1 P2 P3 CNTVCON2 CNTVCO2
READY  ;
DFF: CT2 IN: CK CNTVG3VD OUT: CT2 ;
DFF: CT1 IN: CK CNTVG2VD OUT: CT1 ;
DFF: CT0 IN: CK CNTVG1VD OUT: CT0 ;
DFF: ACVQN3 IN: CK ACVG4VD1 OUT: ACVQN3 ;
DFF: ACVQN2 IN: CK ACVG3VD1 OUT: ACVQN2 ;
DFF: ACVQN1 IN: CK ACVG2VD1 OUT: ACVQN1 ;
DFF: ACVQN0 IN: CK ACVG1VD1 OUT: ACVQN0 ;
DFF: MRVQN3 IN: CK MRVG4VD OUT: MRVQN3 ;
DFF: MRVQN2 IN: CK MRVG3VD OUT: MRVQN2 ;
DFF: MRVQN1 IN: CK MRVG2VD OUT: MRVQN1 ;
DFF: MRVQN0 IN: CK MRVG1VD OUT: MRVQN0 ;
DFF: AX3 IN: CK AM3 OUT: AX3 ;
DFF: AX2 IN: CK AM2 OUT: AX2 ;
DFF: AX1 IN: CK AM1 OUT: AX1 ;
DFF: AX0 IN: CK AM0 OUT: AX0 ;
NOT: P4 IN: ACVQN0 OUT: P4 ;
NOT: CNTVG3VQN IN: CT2 OUT: CNTVG3VQN ;
NOT: ACVPCN IN: START OUT: ACVPCN ;
NOT: CT1N IN: CT1 OUT: CT1N ;
NOT: CNTVG2VQN IN: CT1 OUT: CNTVG2VQN ;
NOT: CNTVCON0 IN: CT0 OUT: CNTVCON0 ;
NOT: CNTVG1VQN IN: CT0 OUT: CNTVG1VQN ;
NOT: P6 IN: ACVQN2 OUT: P6 ;
NOT: P5 IN: ACVQN1 OUT: P5 ;
NOT: P0 IN: MRVQN0 OUT: P0 ;
NOT: P2 IN: MRVQN2 OUT: P2 ;
NOT: P7 IN: ACVQN3 OUT: P7 ;
NOT: P3 IN: MRVQN3 OUT: P3 ;
NOT: P1 IN: MRVQN1 OUT: P1 ;
NOT: AMVS0N IN: INIT OUT: AMVS0N ;
NOT: CNTVCO0 IN: CNTVG1VQN OUT: CNTVCO0 ;
NOT: READY IN: READYN OUT: READY ;
NOT: BMVS0N IN: READYN OUT: BMVS0N ;
NOT: AMVG5VS0P IN: AMVS0N OUT: AMVG5VS0P ;
NOT: AMVG4VS0P IN: AMVS0N OUT: AMVG4VS0P ;
NOT: AMVG3VS0P IN: AMVS0N OUT: AMVG3VS0P ;
NOT: AMVG2VS0P IN: AMVS0N OUT: AMVG2VS0P ;
NOT: AD0 IN: AD0N OUT: AD0 ;
NOT: AD1 IN: AD1N OUT: AD1 ;
NOT: AD2 IN: AD2N OUT: AD2 ;
NOT: AD3 IN: AD3N OUT: AD3 ;
NOT: CNTVG1VD1 IN: READY OUT: CNTVG1VD1 ;
NOT: BMVG5VS0P IN: BMVS0N OUT: BMVG5VS0P ;
NOT: BMVG4VS0P IN: BMVS0N OUT: BMVG4VS0P ;
NOT: BMVG3VS0P IN: BMVS0N OUT: BMVG3VS0P ;
NOT: BMVG2VS0P IN: BMVS0N OUT: BMVG2VS0P ;
NOT: CNTVG3VD1 IN: CNTVCON1 OUT: CNTVG3VD1 ;
NOT: SMVS0N IN: ADSH OUT: SMVS0N ;
NOT: MRVSHLDN IN: ADSH OUT: MRVSHLDN ;
NOT: ADDVC1 IN: ADDVG1VCN OUT: ADDVC1 ;
NOT: SMVG5VS0P IN: SMVS0N OUT: SMVG5VS0P ;
NOT: SMVG4VS0P IN: SMVS0N OUT: SMVG4VS0P ;
NOT: SMVG3VS0P IN: SMVS0N OUT: SMVG3VS0P ;
NOT: SMVG2VS0P IN: SMVS0N OUT: SMVG2VS0P ;
NOT: CNTVG1VZ IN: CNTVG1VZ1 OUT: CNTVG1VZ ;
NOT: AM3 IN: AMVG5VX OUT: AM3 ;
NOT: AM2 IN: AMVG4VX OUT: AM2 ;
NOT: AM1 IN: AMVG3VX OUT: AM1 ;
NOT: AM0 IN: AMVG2VX OUT: AM0 ;
NOT: S0 IN: ADDVG1VP OUT: S0 ;
NOT: BM3 IN: BMVG5VX OUT: BM3 ;
NOT: BM2 IN: BMVG4VX OUT: BM2 ;
NOT: BM1 IN: BMVG3VX OUT: BM1 ;
NOT: BM0 IN: BMVG2VX OUT: BM0 ;
NOT: ADDVC2 IN: ADDVG2VCN OUT: ADDVC2 ;
NOT: S1 IN: ADDVG2VSN OUT: S1 ;
NOT: ADDVC3 IN: ADDVG3VCN OUT: ADDVC3 ;
NOT: S2 IN: ADDVG3VSN OUT: S2 ;
NOT: SM0 IN: SMVG2VX OUT: SM0 ;
NOT: CO IN: ADDVG4VCN OUT: CO ;
NOT: S3 IN: ADDVG4VSN OUT: S3 ;
NOT: SM1 IN: SMVG3VX OUT: SM1 ;
NOT: SM3 IN: SMVG5VX OUT: SM3 ;
NOT: SM2 IN: SMVG4VX OUT: SM2 ;
AND: AMVG5VG1VAD1NF IN: AMVS0N AX3 OUT: AMVG5VG1VAD1NF ;
AND: AMVG4VG1VAD1NF IN: AMVS0N AX2 OUT: AMVG4VG1VAD1NF ;
AND: AMVG3VG1VAD1NF IN: AMVS0N AX1 OUT: AMVG3VG1VAD1NF ;
AND: AMVG2VG1VAD1NF IN: AMVS0N AX0 OUT: AMVG2VG1VAD1NF ;
AND: BMVG5VG1VAD1NF IN: BMVS0N P3 OUT: BMVG5VG1VAD1NF ;
AND: BMVG4VG1VAD1NF IN: BMVS0N P2 OUT: BMVG4VG1VAD1NF ;
AND: BMVG3VG1VAD1NF IN: BMVS0N P1 OUT: BMVG3VG1VAD1NF ;
AND: BMVG2VG1VAD1NF IN: BMVS0N P0 OUT: BMVG2VG1VAD1NF ;
AND: AMVG5VG1VAD2NF IN: AMVG5VS0P A3 OUT: AMVG5VG1VAD2NF ;
AND: AMVG4VG1VAD2NF IN: AMVG4VS0P A2 OUT: AMVG4VG1VAD2NF ;
AND: AMVG3VG1VAD2NF IN: AMVG3VS0P A1 OUT: AMVG3VG1VAD2NF ;
AND: AMVG2VG1VAD2NF IN: AMVG2VS0P A0 OUT: AMVG2VG1VAD2NF ;
AND: ADDVG2VCNVAD1NF IN: AD1 P5 OUT: ADDVG2VCNVAD1NF ;
AND: ADDVG3VCNVAD1NF IN: AD2 P6 OUT: ADDVG3VCNVAD1NF ;
AND: ADDVG4VCNVAD1NF IN: AD3 P7 OUT: ADDVG4VCNVAD1NF ;
AND: MRVG3VDVAD1NF IN: ADSH P3 OUT: MRVG3VDVAD1NF ;
AND: MRVG2VDVAD1NF IN: ADSH P2 OUT: MRVG2VDVAD1NF ;
AND: MRVG1VDVAD1NF IN: ADSH P1 OUT: MRVG1VDVAD1NF ;
AND: BMVG5VG1VAD2NF IN: BMVG5VS0P B3 OUT: BMVG5VG1VAD2NF ;
AND: BMVG4VG1VAD2NF IN: BMVG4VS0P B2 OUT: BMVG4VG1VAD2NF ;
AND: BMVG3VG1VAD2NF IN: BMVG3VS0P B1 OUT: BMVG3VG1VAD2NF ;
AND: BMVG2VG1VAD2NF IN: BMVG2VS0P B0 OUT: BMVG2VG1VAD2NF ;
AND: SMVG5VG1VAD1NF IN: SMVS0N P7 OUT: SMVG5VG1VAD1NF ;
AND: SMVG4VG1VAD1NF IN: SMVS0N P6 OUT: SMVG4VG1VAD1NF ;
AND: SMVG3VG1VAD1NF IN: SMVS0N P5 OUT: SMVG3VG1VAD1NF ;
AND: SMVG2VG1VAD1NF IN: SMVS0N P4 OUT: SMVG2VG1VAD1NF ;
AND: ADDVG2VCNVAD4NF IN: ADDVC1 AD1 P5 OUT: ADDVG2VCNVAD4NF ;
AND: ADDVG2VCNVAD2NF IN: ADDVC1 ADDVG2VCNVOR1NF OUT: ADDVG2VCNVAD2NF ;
AND: MRVG4VDVAD1NF IN: ADSH S0 OUT: MRVG4VDVAD1NF ;
AND: MRVG4VDVAD2NF IN: MRVSHLDN BM3 OUT: MRVG4VDVAD2NF ;
AND: MRVG3VDVAD2NF IN: MRVSHLDN BM2 OUT: MRVG3VDVAD2NF ;
AND: MRVG2VDVAD2NF IN: MRVSHLDN BM1 OUT: MRVG2VDVAD2NF ;
AND: MRVG1VDVAD2NF IN: MRVSHLDN BM0 OUT: MRVG1VDVAD2NF ;
AND: ADDVG2VCNVAD3NF IN: ADDVG2VCNVOR2NF ADDVG2VCN OUT: ADDVG2VCNVAD3NF ;
AND: ADDVG3VCNVAD4NF IN: ADDVC2 AD2 P6 OUT: ADDVG3VCNVAD4NF ;
AND: ADDVG3VCNVAD2NF IN: ADDVC2 ADDVG3VCNVOR1NF OUT: ADDVG3VCNVAD2NF ;
AND: ADDVG3VCNVAD3NF IN: ADDVG3VCNVOR2NF ADDVG3VCN OUT: ADDVG3VCNVAD3NF ;
AND: SMVG2VG1VAD2NF IN: SMVG2VS0P S1 OUT: SMVG2VG1VAD2NF ;
AND: ADDVG4VCNVAD4NF IN: ADDVC3 AD3 P7 OUT: ADDVG4VCNVAD4NF ;
AND: ADDVG4VCNVAD2NF IN: ADDVC3 ADDVG4VCNVOR1NF OUT: ADDVG4VCNVAD2NF ;
AND: ADDVG4VCNVAD3NF IN: ADDVG4VCNVOR2NF ADDVG4VCN OUT: ADDVG4VCNVAD3NF ;
AND: SMVG3VG1VAD2NF IN: SMVG3VS0P S2 OUT: SMVG3VG1VAD2NF ;
AND: SMVG5VG1VAD2NF IN: SMVG5VS0P CO OUT: SMVG5VG1VAD2NF ;
AND: SMVG4VG1VAD2NF IN: SMVG4VS0P S3 OUT: SMVG4VG1VAD2NF ;
OR: ADDVG1VPVOR1NF IN: AD0 P4 OUT: ADDVG1VPVOR1NF ;
OR: ADDVG2VCNVOR1NF IN: AD1 P5 OUT: ADDVG2VCNVOR1NF ;
OR: ADDVG3VCNVOR1NF IN: AD2 P6 OUT: ADDVG3VCNVOR1NF ;
OR: ADDVG4VCNVOR1NF IN: AD3 P7 OUT: ADDVG4VCNVOR1NF ;
OR: CNTVG2VG2VOR1NF IN: CT1 CNTVG2VD1 OUT: CNTVG2VG2VOR1NF ;
OR: CNTVG3VG2VOR1NF IN: CT2 CNTVG3VD1 OUT: CNTVG3VG2VOR1NF ;
OR: ADDVG2VCNVOR2NF IN: ADDVC1 AD1 P5 OUT: ADDVG2VCNVOR2NF ;
OR: ADDVG3VCNVOR2NF IN: ADDVC2 AD2 P6 OUT: ADDVG3VCNVOR2NF ;
OR: ADDVG4VCNVOR2NF IN: ADDVC3 AD3 P7 OUT: ADDVG4VCNVOR2NF ;
NAND: READYN IN: CT0 CT1N CT2 OUT: READYN ;
NAND: AD0N IN: P0 AX0 OUT: AD0N ;
NAND: AD1N IN: P0 AX1 OUT: AD1N ;
NAND: AD2N IN: P0 AX2 OUT: AD2N ;
NAND: AD3N IN: P0 AX3 OUT: AD3N ;
NAND: CNTVCON2 IN: CT2 CNTVCO1 OUT: CNTVCON2 ;
NAND: CNTVCON1 IN: CT1 CNTVCO0 OUT: CNTVCON1 ;
NAND: ADDVG1VCN IN: AD0 P4 OUT: ADDVG1VCN ;
NAND: CNTVG2VZ1 IN: CT1 CNTVG2VD1 OUT: CNTVG2VZ1 ;
NAND: CNTVG1VZ1 IN: CT0 CNTVG1VD1 OUT: CNTVG1VZ1 ;
NAND: CNTVG3VZ1 IN: CT2 CNTVG3VD1 OUT: CNTVG3VZ1 ;
NAND: ADDVG1VP IN: ADDVG1VPVOR1NF ADDVG1VCN OUT: ADDVG1VP ;
NAND: CNTVG2VZ IN: CNTVG2VG2VOR1NF CNTVG2VZ1 OUT: CNTVG2VZ ;
NAND: CNTVG3VZ IN: CNTVG3VG2VOR1NF CNTVG3VZ1 OUT: CNTVG3VZ ;
NAND: ACVG1VD1 IN: ACVPCN SM0 OUT: ACVG1VD1 ;
NAND: ACVG2VD1 IN: ACVPCN SM1 OUT: ACVG2VD1 ;
NAND: ACVG4VD1 IN: ACVPCN SM3 OUT: ACVG4VD1 ;
NAND: ACVG3VD1 IN: ACVPCN SM2 OUT: ACVG3VD1 ;
NOR: INIT IN: CT0 CT1 CT2 OUT: INIT ;
NOR: CNTVCO1 IN: CNTVG2VQN CNTVCON0 OUT: CNTVCO1 ;
NOR: ADSH IN: READY INIT OUT: ADSH ;
NOR: CNTVG2VD1 IN: READY CNTVCON0 OUT: CNTVG2VD1 ;
NOR: CNTVCO2 IN: CNTVG3VQN CNTVCON1 OUT: CNTVCO2 ;
NOR: AMVG5VX IN: AMVG5VG1VAD2NF AMVG5VG1VAD1NF OUT: AMVG5VX ;
NOR: AMVG4VX IN: AMVG4VG1VAD2NF AMVG4VG1VAD1NF OUT: AMVG4VX ;
NOR: AMVG3VX IN: AMVG3VG1VAD2NF AMVG3VG1VAD1NF OUT: AMVG3VX ;
NOR: AMVG2VX IN: AMVG2VG1VAD2NF AMVG2VG1VAD1NF OUT: AMVG2VX ;
NOR: BMVG5VX IN: BMVG5VG1VAD2NF BMVG5VG1VAD1NF OUT: BMVG5VX ;
NOR: BMVG4VX IN: BMVG4VG1VAD2NF BMVG4VG1VAD1NF OUT: BMVG4VX ;
NOR: BMVG3VX IN: BMVG3VG1VAD2NF BMVG3VG1VAD1NF OUT: BMVG3VX ;
NOR: BMVG2VX IN: BMVG2VG1VAD2NF BMVG2VG1VAD1NF OUT: BMVG2VX ;
NOR: CNTVG2VD IN: CNTVG2VZ START OUT: CNTVG2VD ;
NOR: CNTVG1VD IN: CNTVG1VZ START OUT: CNTVG1VD ;
NOR: CNTVG3VD IN: CNTVG3VZ START OUT: CNTVG3VD ;
NOR: ADDVG2VCN IN: ADDVG2VCNVAD2NF ADDVG2VCNVAD1NF OUT: ADDVG2VCN ;
NOR: MRVG4VD IN: MRVG4VDVAD2NF MRVG4VDVAD1NF OUT: MRVG4VD ;
NOR: MRVG3VD IN: MRVG3VDVAD2NF MRVG3VDVAD1NF OUT: MRVG3VD ;
NOR: MRVG2VD IN: MRVG2VDVAD2NF MRVG2VDVAD1NF OUT: MRVG2VD ;
NOR: MRVG1VD IN: MRVG1VDVAD2NF MRVG1VDVAD1NF OUT: MRVG1VD ;
NOR: ADDVG2VSN IN: ADDVG2VCNVAD4NF ADDVG2VCNVAD3NF OUT: ADDVG2VSN ;
NOR: ADDVG3VCN IN: ADDVG3VCNVAD2NF ADDVG3VCNVAD1NF OUT: ADDVG3VCN ;
NOR: ADDVG3VSN IN: ADDVG3VCNVAD4NF ADDVG3VCNVAD3NF OUT: ADDVG3VSN ;
NOR: SMVG2VX IN: SMVG2VG1VAD2NF SMVG2VG1VAD1NF OUT: SMVG2VX ;
NOR: ADDVG4VCN IN: ADDVG4VCNVAD2NF ADDVG4VCNVAD1NF OUT: ADDVG4VCN ;
NOR: ADDVG4VSN IN: ADDVG4VCNVAD4NF ADDVG4VCNVAD3NF OUT: ADDVG4VSN ;
NOR: SMVG3VX IN: SMVG3VG1VAD2NF SMVG3VG1VAD1NF OUT: SMVG3VX ;
NOR: SMVG5VX IN: SMVG5VG1VAD2NF SMVG5VG1VAD1NF OUT: SMVG5VX ;
NOR: SMVG4VX IN: SMVG4VG1VAD2NF SMVG4VG1VAD1NF OUT: SMVG4VX ;