ELEC4200 Digital System Design

Introduction to ISE & ModelSim (Lab0)

Professor: Charles E. Stroud

Tutorial by: Gefu Xu

Synthesize the Design

1)   First select the design to be synthesized. In the Sources Window, select Mux_Schematic and then choose Implementation (note that the figure below which shows ¡°Syntehsis/Implementation¡± in the ¡°Sources for¡± menu was taken from ISE8.2). In the Processes Window, select Synthesize-XST, right click mouse and select Run.

 

Note that this step does not actually implement the design in the FPGA but rather produces an intermediate design that will then be implemented for the specific FPGA in a later step.

 

 

2) Before we actually implement the design, we need to add a constraints file to our design. This constraints file contains the pin assignment information so that ISE can associate the right physical pins for the switches and LEDs on the Spartan 3 PCB with the primary inputs/outputs in our design (so that we can verify the design in hardware).  Remember to set the location a flash drive on the PC in the lab to maximize performance.

 

 

 

 

Run I/O Pin Place (post-synthesis)

 

00_9.JPG

 

Type in the pin locations for all primary inputs and outputs and save. In this example, we assign Din0 to pin F12, Din1 to pin G12, and Sel to pin H14, these pins correspond to switches SW0 through SW2, respectively, on the Spartan 3 PCB.  We assign Dout to pin K12 which corresponds to LED LD0 on the PCB.  This will allow you to manipulate the three switches to apply input values to the circuit while observing the output response on the LED to verify the correct operation of the design in hardware.

 

00_10.JPG

 

Ensure that PlanAhead is running in full-screen mode and that you can see the I/O ports tab. Clicking on ¡°Scalar ports¡± brings a dropdown list of the circuit¡¯s nets. Right click on a net and then click ¡°Place I/O ports in an I/O Bank¡± if you wish to use the drag and drop pictorial matrix of pins. However, it will most likely by more conviencent to simply click on the net name (Din0, Sel, etc.) and then entering the site using the menu directly above the I/O ports tab.

 

3) After the constraints file has been created, right click on Implement Design and select Run.

 

4) Next right click on Generate Programming File and select Run.

 

Finally, a FPGA configuration data (*.bit) file is generated.

 

Note that there are a number of important and interesting aspects of the Synthesis, Implement Design, and Generate Programming File steps that will be discussed in later tutorials.