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ELEC4200 Digital System Design Introduction to ISE & ModelSim (Lab0) Professor: Charles E. Stroud Tutorial by: Gefu Xu |
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Design Verification 1) First, select the design to be
simulated. In the Sources Window, select Mux_Schematic
and then choose Behavioral Simulation.
In the Processes Window, expand the ModelSim
Simulator icon and then right click on Simulate Behavioral Model and choose Run. If you have
problems getting ModelSim to run see the GTAs Frequently
Asked Questions for assistance with common ModelSim problems.
It is possible that
your path to the ModelSim executable is incorrect. Ensure that it is correct
by going to Edit
> Preferences > Integrated Tools and ensure that the path is indeed correct for your
system.
A ModelSim simulation
window will pop-up as shown below (note that there are brief comments added
to this figure to describe the four sub-windows).
2) Now we will force all input signals one by one to
the logic values for the simulation. The objective here is to apply all
input values that would be needed to ensure there are no errors (bugs) in the
design and, as a result, you must carefully consider what those values should
be. For a small combinational logic circuit (say 6 inputs or less) for
example, all possible input combinations will ensure that there are no design
errors. The basic force
statement format is: force signal-name state-value time . For
example, force Din0 0 100, 1 200
means signal Din0 is forced to logic 0 at 100 time units and is forced to
logic 1 at 200 time units. After forcing all
input signals, we will use command run
N time-units (e.g. run 300) to
start a simulation. The simulation results will be shown in Objects Window and Waveform Window. Check these results
out to verify your design.
3) We also can add
forces on signals in other ways instead of typing force commands in the
command window one by one. For example, right click on the signal name and
select force/clock. Then type in
the force value you want and the duration for this force signal, and then
click OK. Notice when we add
forces in this way, the real force commands will also be printed in the
bottom window (command window). You can copy those commands and paste them in
a DO file for later use. The following two
figures demonstrate how to add a force (logic 1) to net Din0. This force signal will remain for 1000 time units.
The following two
figures demonstrate how to add a clock (with 50% duty cycle and period of 100
time units) to net Sel. This clock
signal will continue cycling for 1000 time units.
4) We can also edit
a force file instead of forcing signals in command window one by one. For
example, if you type the following text into a file and save the file as mux.do, then you can directly execute
this do file to launch a
simulation. In this example, you should also note the use of the repeat force option rather than
specifying every time a signal changes. In this example, the three
inputs will be square waves with 50% duty cycle where Sel has a 40 time unit
period, Din0 has an 80 time unit
period, and Din1 has a 160 time
unit period (this produces all possible combinations of the three inputs).
Also note that the run
command with result in a simulation of 200 time units such that the input
sequence will begin to repeat after 160 time units.
4) If any incorrect
results occur during simulation, you need to debug errors in the design. Note
the place (Net Name or Instance Name) where errors occur and use find to local those points in the
schematic. Repeat the simulation (and debug) process until the circuit
gives the correct output responses for all input values, at which time you
circuit has been verified via simulation.
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