ELEC4200 Digital System Design Introduction to ISE & ModelSim (Lab0) Professor: Charles E. Stroud Tutorial by: Gefu Xu

VHDL Entry 1) If we choose VHDL as the design entry, we can use any text editor tool to create and edit the VHDL code and then add the VHDL file into an ISE project. For example, you can open Notepad, type (or cut and paste) in the following VHDL code, and save the model as a file such as mux.vhd (be sure to remove any .txt extension that Notepad adds at the end of the file name). library IEEE; use IEEE.std_logic_1164.all; entity mux_vhdl is port (Din0,Din1,Sel: in STD_LOGIC; Dout: out STD_LOGIC); end entity mux_vhdl; architecture RTL of mux_vhdl is begin Dout <= (Din0 and not Sel) or (Din1 and Sel); end architecture RTL; 2) Create a new project (as described for the schematic capture process but this time use a different project name) and add the existing VHDL file (mux.vhd) to this project as follows. 3) VHDL can also be entered directly in ISE and the benefit is that there are a number of modeling aids, including color indications of keywords. First, select New Source in the Project menu. Choose the source type as VHDL Module, type in a file name (e.g. mux_vhdl) and click Next. Remember to set the location to the C: drive on the PC in the lab to maximize performance. Type in all Port Names, select the Direction (type) for each port and click Next. Note that you can also indicate busses for bit_vectors (std_logic_vectors). This page displays the summary of this new created VHDL file. Now an empty VHDL file has been created which already has the entity and skeleton of the architecture. Type in your VHDL codes in architecture and complete your design. After you finish the design, save the file. For the 2-to-1 MUX simply type (or cut and paste) the following line for your VHDL code: Dout <= (Din0 and not Sel) or (Din1 and Sel);