ELEC4200 Digital System Design

Introduction to ISE & ModelSim (Lab0)

Professor: Charles E. Stroud

Tutorial by:Gefu Xu

Lab Instruction

Objectives:

In this Lab exercise, we will design a 2-to-1 multiplexer (MUX) using the following two types of design entry:

1) schematic capture using ISE (Xilinx Corp.)

2) VHDL entry using any text editor

After design entry (either schematic capture or VHDL entry), ModelSim (Mentor Graphic Corp.) will be used to simulate and verify the design (with debugging performed as needed). After the design is fully verified, we will use ISE to synthesize the design into a Spartan 3 FPGA configuration data file which will then be downloaded onto a Spartan 3 printed circuit board (PCB) where the implemented design will be verified.

Design Specification:

The 2-to-1 multiplexer has three inputs (two data inputs and one select input) and one data output.

Data input:	Din0, Din1
Select input:	Sel
Data output:	Dout
Logic Function: when Sel=0, Dout=Din0 when Sel=1, Dout=Din1
Boolean Logic Equation: Dout = Din0 * Sel¢ + Din1 * Sel

Basic Design Steps of this Lab Exercise:

Create a New Project using ISE

Schematic capture using ISE

Design Verification by simulation of the design using ModelSim

Synthesize Design to an FPGA configuration data file using ISE

Download & Verify Design by programming the FPGA on the PCB and verifying correct operation of the design

Now repeat the steps above but this time using a VHDL file (that will be provided for you in the VHDL portion of the tutorial)

To proceed through this tutorial click on the box to the left for each step in the design process, following the arrows through the appropriate path (schematic capture or VHDL)