Benchmark Circuits for Analog and Mixed Signal Testing
This project was sponsored by U.S. Air Force Research Laboratory

Introduction

The IEEE 1997 International Test Conference benchmark circuits are a set of analog and mixed-signal circuits provided for the evaluation and performance of different testing approaches.  However, the fault models for these benchmark circuits, along with a list of standard faults and range of acceptable component variations were not specified but are a major concern in analog device testing. This site gives fault models for ITC'97 benchmark circuits and establishes acceptable component variations.  The set of benchmark circuits consists of some of the circuits taken from ITC'97 benchmark circuits [1] along with others from different sources like Statistical Fault Analyzer (SFA) [5][6].  These circuits are listed in the following table along with their source and the number of components (Rs, Cs, BJTs, and MOSFETs) and number of operational amplifiers that constitute the benchmark circuit.  Click on the links in the table to obtain more detailed information for a given circuit.

Benchmark Circuits

Name of Circuit

Source

Number of components

Operational Amplifier #1

ITC’97 [1]

11

Continuous-Time State-Variable Filter

ITC’97 [1]

9 & 3 opamps

Operational Amplifier #2

ITC’97 [1]

10

Leapfrog Filter

ITC’97 [1]

17 & 6 opamps

Digital-to-Analog Converter

ITC’97 [1]

34 & 1 opamp

Differential Amplifier

SFA [5][6]

9

Comparator

SFA [5][6]

3 & 1 opamp

Single Stage Amplifier

SFA [5][6]

6

Elliptical Amplifier

SFA [5][6]

22 & 3 opamps

Low-Pass Filter

Lucent Tech.

4 & 1 opamp

For references, see the original paper on benchmark circuits from Proc. IEEE Southeast Regional Conference, 1999.

Fault Models

Fault models for analog and mixed signal circuits can be classified into two categories: catastrophic faults (sometimes called hard faults) and parametric faults (sometimes called soft faults).  A catastrophic fault model is analogous to the stuck-at fault model in the digital domain in that the terminals of the component can be stuck-open or stuck-short.  Parametric faults, on the other hand, are deviations of component parameters that result in performance out of acceptable limits. Parametric faults can be simulated as a variation of a component parameter which is out of specified tolerance limits. As will be discussed in Simulation method, we establish acceptable component parameter variations using a normal distribution and specify the 1-sigma value (expecting the acceptable variation to be up to 3-sigma).  Therefore we specify parametric faults at the +/- 6-sigma values for high and low parametric fault values, respectively. The catastrophic fault models for individual components are described below.

Stuck-open faults are hard faults in which the component terminals are out of contact with the rest of the circuit creating a high resistance at the incident of fault in the circuit.  These faults can be simulated by adding a high resistance in series (Rs=100megohm) with the component to be faulted.  A stuck-short fault, on the other hand, is a short between terminals of the component (effectively shorting out the component from the circuit).  This type of fault can be emulated by connecting a small resistor in parallel (Rs=1ohm) with the component.  Stuck-open and stuck-short faults can be emulated in a resistor or capacitor as illustrated in Figure 1.  A MOSFET stuck-on and stuck-off fault can be emulated using the stuck-open and stuck-short fault model as shown in Figure 1. For the fault-free case Rs=1ohm and Rp=100megohm.

Another fault model is used for bipolar junction transistors (BJTs).  The BJT can have 3 stuck-open faults (at the base, collector, and emitter terminals) 3 stuck-short faults (between base-collector, base-emitter, and collector-emitter).  These stuck-open and stuck-short faults are emulated in the same manner using 3 series resistors Rb, Rc, and Re, for the stuck-open fault (like Rs above) and 3 parallel resistors Rbc, Rbe and Rce (like Rp above), as shown in Figure 1.  In addition, the BJT has two soft faults for the value of beta.

Fault Model

Rs

Rp

Fault free

1 W

100 MW

Stuck-short

1 W

1 W

Stuck-open

100 MW

100MW

BJT Fault Model

Rb

Rc

Re

Rbc

Rbe

Rce

Fault free

1 W

1 W

1 W

100 MW

100 MW

100 MW

Base-open

100 MW

1 W

1 W

100 MW

100 MW

100 MW

Collector-open

1 W

100 MW

1 W

100 MW

100 MW

100 MW

Emitter-open

1 W

1 W

100 MW

100 MW

100 MW

100 MW

Base-collector short

1 W

1 W

1 W

1 W

100 MW

100 MW

Base-emitter short

1 W

1 W

1 W

100 MW

1 W

100 MW

Collector-emitter short

1 W

1 W

1 W

100 MW

100 MW

1 W

Figure 1.  Hard Fault Models

With this standard set of faults models we also obtain a standard set of faults. The total number of hard faults in an analog circuit is:  NHF = 2(R+C+M) + 6B

where R= number of resistors, C= number of capacitors, M= number of MOSFETs and B = number of BJTs in the given circuit.

The number of soft faults is:  NSF = 2(R+C) + 2B

Simulation Method

A circuit is designed to meet the tolerances associated with the specific requirement.  Due to the very nature of the manufacturing process and working environment of the designed circuit, the values of the parameters often change.  These variations are acceptable as long as circuit response is within specified limits.  A known range of acceptable values for a circuit component parameter is necessary to establish the fault-free behavior for a given circuit, which can then be used to detect a fault.  To analyze the effects of circuit component parameter variations on the behavior of a circuit, Monte-Carlo analysis is performed.

Monte-Carlo analysis uses a random number generator to generate different kinds of functions like normal and uniform distributions.  The normal distribution was chosen to generate statistical variation of component values in order to specify the amount of acceptable variation on each component using standard deviation or 1-sigma.  This specification, in turn, assumes the component will vary up to 3-sigma yet the analog circuit will continue to operate within the system specification.  We chose as a default system specification, a maximum deviation in the gain and phase response of the circuit to be within 10% of the gain and phase response of the circuit when using nominal component values.

In order to facilitate comparison of results like fault coverage through different testing methods for the parametric faults, we propose to use standard soft faults.  The 6-sigma point on the either side of the nominal value is defined as a standard parametric fault or soft fault for each component, where 1sigma point represents the amount of acceptable variation in Gaussian distribution.