Practically Realizing Random Access Scan

Speaker: Anand S. Mudlapur

Date: Tuesday, November 15, 2005

Time: 3:00 pm

Room: Broun 203

Abstract:

The number of clock cycles in a serial scan (SS) test is often prohibitive as the number of Flip-Flops (FF) increases. Besides, scan-in and scan-out sequences result in unwanted circuit activity. This increases the test power enormously. The scan process activates all FFs in the scan chain, although very few FFs need to be set for a targeted fault and only a subset of all the FFs needs to be observed. A technique known as Random Access Scan (RAS) can solve these problems. Here every FF is addressed uniquely.

In RAS, only the required number of FFs are set or reset for a given test and this reduces the set up time of FFs significantly. Due to the flexibility of setting any FF randomly, the test power drastically reduces to a bare minimum. Thus two orthogonal problems can be addressed using a single technique namely RAS. These advantages come at a cost of increased area overhead and this is often unacceptable.

In this work, we have addressed the problem in such a way that the implementation is close to feasibility and the additional area overhead is justified. We have developed a new RAS cell, which minimizes the number of signals otherwise routed to it compared to earlier designs. This improvement saves a lot of silicon area.

Another contribution that we have done in this work is that we have designed our RAS cell with out a scan-in signal and introduced an operation called `toggle'. Our toggle FF toggles its state when addressed and hence any desired state can be achieved by just addressing it. The scan out structure is also designed in such a way that when a FF is addressed or toggled, the value that existed in the FF is read out. This is done using a hierarchical topology. A bus structure is used to drive the data from the FFs to a primary output. Considering a reasonable drive capability we have come up with a segmented scheme such that, the size of the bus being driven is kept reasonable.

The FFs are addressed using a grid structure with a row and column decoder. We evaluated different decoding schemes and concluded that the grid scheme evaluated to the least routing overhead compared to others. The intersection of a row and column line addresses a FF in the scan mode of operation. The addresses to the decoders are provided using the primary input pins.

Using the above design we have shown that the test vector size can be reduced by 60% compared to single chain serial scan and the test power saving is 99% compared to serial scan. We also provide an algorithm to further decrease the test vector length. Our aim here is to address the problems of serial scan and come up with a feasible low cost solution to it. Recent advances in this field are also reviewed attempting to motivate researchers to come up with novel solutions to the problem.