Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits

Speaker: Fei Hu

Date:Wednesday, November 16, 2005

Time: 3:00 pm

Room: Broun 235

Abstract:

Power dissipation is an increasingly critical issue in modern VLSI design and testing. Previously, linear programming (LP) based methods have been proposed for optimization of circuits for low power dissipation. However, as the transistor size shrinks, variations in the device and circuit parameters increase. Under the existence of process-variations, a circuit optimized by previous techniques will not be able to maintain the low power dissipation.

In this dissertation, we investigate dynamic power optimization techniques that are resistant to the process variation. That is, the power dissipation of the optimized circuit should maintain low power dissipation even if certain degree of process-variation exists. We consider process-variation in terms of the delay variations and classify them into the inter-die and intra-die variations. We prove that the inter-die variation has negligible effect on the power dissipation of the circuit.

We propose two new linear programming (LP) models to obtain solutions that continue to maintain low power dissipation under the process variation. The two LP models are based on worst-case timing analysis and statistical timing analysis, respectively. We also consider input-vector specific optimization to reduce the number of delay elements inserted into the circuit. Our experimental results show that our LP models can obtain a more process-variation-resistant solution in terms of both power dissipation and critical delay. That is, our optimization is also able to suppress the deviation of critical delay from its nominal value under the process-variation. We use a trade-off between the robustness (process-variation-resistance) and the circuit performance in terms of the critical delay. Our experimental results on ISCAS'85 benchmarks show complete suppression of power variation for small circuits and process-variations. Up to 53\% reduction of power variation and 40\% reduction of the delay variation are obtained for those large circuits under a large process-variation and certain critical delay requirement. In our experiments, the application of input-specific optimization to our LP model is able to reduce the number of buffers by up to 63\%.

Our work explores a new aspect of generalized dynamic power optimization techniques. We propose a LP based method to improve a design under the existence of process-variation. The resulting circuit is more process-variation-resistant in terms of both power dissipation and critical delay. The merit of our solution will be more and more vital as technology keeps marching forward.