Date
|
Speaker (w/ link to abstract)
|
Topic (w/ link to presentation slides after
seminar date)
|
January19
|
AUBIST
Lab Group
|
Current Research in Built-In Self-Test
for SoCs and FPGAs
|
January
26
|
Dr.
Adit Singh
|
Delay Detection in the Slack Interval:
An Alternate Delay Test Methodology
|
February
2
|
Dr. Vishwani Agrawal
|
Implication Graphs and Logic Testing
|
February
9
|
Mr.
Raja Sandireddy
|
Hierarchical Fault Collapsing for Logic Circuits
|
February
11*
|
Dr. Chin-Long Wey,
National Central Univ, Taiwan
|
Silicon
Island Project and IT Product Development in Taiwan
|
February
17
|
Dr. Abhijit Chatterjee,
Georgia Tech
|
Low Cost Alternate Testing of Analog/Mixed-Signal/RF Circuits
|
March
2
|
Mr. Fei Hu
|
VLSI Power Estimation & Dual-Transition Glitch
Filtering in Probablistic Simulation
|
March
9
|
Mr.
Ayoush Dixit
|
Overview
of
Circular BIST & Modifying Multi-Mode Scan to Handle Hard-to-Detect
Faults and X-States
|
March
16
|
Dr.
Chuck Stroud
|
BIST-Based
Fault Diagnosis for Embedded Cores in Systems-on-Chip
|
March
23
|
Mr. Srinivas Garimella (MS
Thesis Defense)
|
Built-In
Self-Test for Regular Structure Embedded Cores in System-on-Chip
|
April
6
|
Mr.
Dayu Yang (PhD Research Proposal)
|
Design
of Direct Digital Frequency Synthesizer for Analog Circuit Test
|
April
13
|
Mr.
Alok Doshi
|
Test
Generation Using Independent and Concurrently Testable Faults
|
April
20
|
Ms.
Yuanlin Lu
|
Minimizing
Leakage Power in Dual-Threshold CMOS Circuits Using Integer Linear
Programming
|
April
27
|
Nitin
Yogi, John Sunwoo,
Sachin Dhingra,
Sudheer Vemula
|
IEEE
North Atlantic Test Workshop presentations on SoC/FPGA Testing and
Built-In Self-Test
|