The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.
The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:
the Testing Group at Auburn:
Vishwani Agrawal - Design for Testability (DFT) and low-power design
Foster Dai - mixed-signal and analog design and testing
Vic Nelson - ASIC/FPGA testing and fault tolerance
Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)
Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2005:
Coordinator: Dr. Chuck Stroud

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Aug. 24	Mr. Sachin Dhingra & Mr. Sudheer Vemula	Current Research in Built-In Self-Test for SoCs and FPGAs
Sept. 7	Dr. Chuck Stroud	BIST for FPGA Cores in SoCs Using Embedded Processor Dynamic Reconfiguration
Sept. 14	Ms. Yuanlin Lu	Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming  for Vth Assignment and Path Balancing
Sept. 21	Dr. Vic Nelson	VLSI/FPGA Design and Test CAD Tool Flow in Mentor Graphics
Sept. 28	Mr. Fei Hu	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Oct. 5	Dr. Chuck Stroud	On-Chip Automatic Analog Functional Testing and Measurements
Oct. 12	Dr. Adit Singh	A Self-Timed Structural Test Methodology for Timing Anomalies Due to Defects and Process Variations
Oct. 19	Mr. Anand Mudlapur	A Random Access Scan Architecture to Reduce Hardware Overhead
Oct. 26	Mr. Alok Doshi	Concurrent Test Generation
Nov. 2	Mr. Gefu Xu	Delay Defect Characterization Using Low Voltage Test
Nov. 15	Mr. Anand Mudlapur (MS Thesis Defense)	Practically Realizing Random Access Scan
Nov. 16	Mr. Fei Hu (PhD Dissertation Defense)	Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits
Nov. 30	Mr. Kalyana Kantipudi	On the Size and Generation of Minimal N-Detection Tests