The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

This seminar series sponsored by:
the Testing Group at Auburn:
Vishwani Agrawal - Design for Testability (DFT) and low-power design
Foster Dai - mixed-signal and analog design and testing
Vic Nelson - ASIC/FPGA testing and fault tolerance
Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)
Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2004:
Coordinator: Dr. Chuck Stroud

Date	Speaker	Topic (w/ link to presentation slides after seminar date)
September 15	Dr. Chuck Stroud - IVANed	Built-In Self-Test for System-on-Chips: A Case Study - IVANed
September 22	Mr. Nitin Yogi	P1500 wrapper design for System-on-Chip testing
September 29	Dr. Adit Singh	Multi-Mode Scan: Test-per-Clock BIST for IP Cores
October 6	Dr. Chuck Stroud	Built-In Self-Test for System-on-Chips: A Case Study
October 13	Mr. Anand Mudlapur	Practically Realizing Random Access Scan
October 20	Mr. Jonathan Harris	BIST for Field Programmable Gate Array Cores in System-on-Chip
November 3	Dr. Foster Dai	Mixed-Signal Built-In Self-Test
November 10	Mr. Raja Sandireddy	Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
November 17	Dr. Vishwani Agrawal	Spectral Testing

Web page coordinator: Chuck Stroud