The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

 

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

 

Spring 2009 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Adit Singh

Invitation: If you are interested in presenting a seminar during Spring 2009, please contact the coordinator.

Notes: The following is a tentative schedule for Spring 2009.  The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date

Speaker

Topic (w/ link to presentation slides after seminar date)

Jan. 7

No Seminar

 

Jan. 14

No Seminar

Memorial Service for Dr. Hodel

Jan. 21

Chuck Stroud

Built-In Self-Test, Measurement, and Compensation of Mixed-Signal ICs

Jan. 28

 Adit Singh

 Noise and Variability Challenges in Delay Testing (ETS09)

Feb. 4

 Asfaq Shakoor

 Fault Detection and Diagnostic Test Set Minimization (MS Defense)

Feb. 11

 Asfaq Shakoor

 A Primal-Dual Solution to Minimal Test Generation Problem

Feb. 18

 Victor Nelson

 IC Testing with the IMS “Logic Master XL-60”

Feb. 25

 Chaitanya Bandi

 Fully Configurable Hierarchical Transaction Level Verifier for Functional Verification

Mar. 4

 

 IEEE Southeast Symp. on System Theory Paper Presentations

Mar. 11

M. Pulukuri, J. Qin, & J. Yao

IEEE Southeast Symp. on System Theory Paper Presentations

Mar. 18

No Seminar

Spring Break Week

Mar. 25

Brad Dutton

International Conf. on Computers and Their Applications Paper Presentations

Apr. 1

Brooks Garrison

Built-In Self-Test of Embedded RAMs in Virtex-5 FPGAs (MS defense)

Apr. 8

Priyadharshini S 

Measurement of Maximum Clock Frequency of a VLSI Chip using the IMS Logic Master XL-60

Apr. 15

 Yu Zhang

Diagnostic Testing with ATE

Apr. 22

Jia Yao

Built-In Self-Test of Routing Resources in Virtex-4 FPGAs (MS defense)

Apr. 29

Mary Pulukuri

Built-In Self-Test of Embedded DSPs in FPGAs (MS Defense)

 

Links to previous semesters of the VLSI Design & Test Seminar Series:

Fall 2008: Coordinator Chuck Stroud

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud