#******************************************************
# General sythesis script for Synopsis
# Based on sample script in Eric Brunvand book
#
# First part of the file has design-specific info
# Second part does not need to be changed
#
# Invoke with:
#     -f synScript
#
# Assumes variables defined in .synopsys_dc.setup file
#    SynopsysInstall = path to Synopsys install directory
#    synthetic_library = designware files
#    symbol_library = logic symbols for making schematics
#
###############################################
# Set these paramters for each specific design
###############################################
# list of HDL files in the design
set myFiles [list \
  ../src/alu.vhd \
  ../src/shiftreg.vhd \
  ../src/mux.vhd \
  ../src/dcontrol.vhd \
  ../src/divider.vhd \
  ]
set fileFormat vhdl		;# verilog or VHDL
set basename divider		;# Top-level module name
set runname 1   		;# Run-specific name appended to output files
set myClk clk   		;# Name of the clock
set maxArea 2000		;# Area constraint

# Timing and loading information
set maxPath_ns  800		;# max path delay from inputs to outputs
set myPeriod_ns 2000		;# desired period in ps (sets speed goal)
set myInDelay_ns 0		;# delay from clock to inputs valid
set myOutDelay_ns 0		;# delay from clock to outputs valid
set myInputBuf INVERT		;# name of cell driving the inputs
set myLoadLibrary vtvt_tsmc250.db	;# name of library cell comes from
#set myLoadPin INVERT		;# name of pin that the outputs drive

# 1 if we want the file, 0 otherwise
set write_v   1		;# compiled structural Verilog file
set write_ddc 1		;# compiled file in ddc format
set write_sdf 1		;# sdf file for back-annotated timing sim
set write_sdc 1		;# sdc contraint file for place and route
set write_rep 1		;# report file from compilation
set write_pow 1		;# report file for power estimation

# Compiler switches...
set useUltra 1			;# 1 for compile_ultra, 0 for compile
set mapEffort1 medium		;# For non-ultra compile - 1st pass
set mapEffort2 high		;# For non-ultra compile - 2nd pass
set useUngroup 1		;# 0 if no flatten, 1 if flatten

###################################################
# Set some system-level things
#
define_design_lib WORK -path ./syn

set search_path [concat "." $search_path ]

# Library list
set link_library   [concat [concat "*" $target_library] $synthetic_library]


#########################################################################
# Below here should not need to be changed
#########################################################################

# Analyze and elaborate the files
analyze -format $fileFormat -lib WORK $myFiles
elaborate $basename -lib WORK -update
current_design $basename

# Link design parts together, and make unique copies of replicated modules
link
uniquify

# Create area constraint
set_max_area $maxArea
set_max_delay $maxPath_ns -to [all_outputs]

# Create clocks and set other constraings
create_clock -period $myPeriod_ns $myClk

#set_driving_cell -library $myLoadLibrary -lib_cell $myInputBuf [all_inputs]

# Set the input and output delay relative to myClk
set_input_delay $myInDelay_ns -clock $myClk [all_inputs]
set_output_delay $myOutDelay_ns -clock $myClk [all_outputs]

# Set loads of the outputs in terms of the load of the next cell they will drive
# Also try to fix hold time issues
#set_load [load_of [format "%s%s%s%s%s" $myLoadLibrary "/" $myInputBuf "/" $myLoadPin]] [all_outputs]
set_fix_hold $myClk

# Fix problem of assign statements left in structural file
# But - inserts pairs of inverters for feedthroughs
set_fix_multiple_port_nets -all -buffer_constants

# Compile the design
if { $useUltra == 1 } {
   compile_ultra
} else {
   if { $useUngroup == 1 } {
      compile -ungroup_all -map_effort $mapEffort1
      compile -incremental_mapping -map_effort $mapEffort2
   } else {
      compile -map_effort $mapEffort1
      compile -incremental_mapping -map_effort $mapEffort2
   }
}

check_design
report_constraint -all_violators

#--------------------------------------
# Write the results
#--------------------------------------
set filebase [format "%s%s" [format "%s%s" $basename "_"] $runname]

# structural verilog
if { $write_v == 1 } {
   set filename [format "%s%s" $filebase ".v"]
   write -format verilog -hierarchy -output $filename
}
#   redirect change_names \
#       { change_names -rules verilog -hierarchy -verbose }

# sdf file for back-annotated verilog sim
if { $write_sdf == 1 } {
   set filename [format "%s%s" $filebase ".sdf"]
   write_sdf -version 1.0 $filename
}

# timing constraints file for place and route program
if { $write_sdc == 1 } {
   set filename [format "%s%s" $filebase ".sdc"]
   write_sdc $filename
}

# Synopsys database format to read back late in XG mode
if { $write_ddc == 1 } {
   set filename [format "%s%s" $filebase ".ddc"]
   write -format ddc -hierarchy -o $filename
}

# Report on the results from synthesis
if { $write_rep == 1 } {
   set filename [format "%s%s" $filebase ".rep"]
   redirect $filename { report_timing}
   redirect -append $filename { report_area }
}

# Report the power estimate from synthesis
if { $write_pow == 1 } {
   set filename [format "%s%s" $filebase ".pow"]
   redirect $filename { report_power}
}

quit