ELEC 5250/6250 - Computer-Aided Design of Digital Circuits

Fall Semester, 2011

Instructor: Victor P. Nelson, Professor of ECE

Syllabus: ELEC 5250/6250

Reference Material:

• Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Hubert Kaeslin, Cambridge University Press, 2008.
• Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand, Addison Wesley, 2010 (soft cover)
• CMOS Circuit Design, Layout, and Simulation, 2^nd Ed., R. Jacob Baker, Wiley-Interscience, 2008
• CMOS VLSI Design, 3^rd Ed., Neil H.E. Weste and David Harris, Addison Wesley, 2005.
• Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley Longman, Inc., 1997 (2008 Soft Cover edition available at Amazon.com and other places)
• Other resources at EDACafe: http://www.edacafe.com/
• International Technology Roadmap for Semiconductors: http://www.itrs.net/Links/2010ITRS/Home2010.htm

Course Lectures & Related Slides:

• Lecture 1 (8/18/11) - ASIC Technology Overview
• Lecture 2 (8/23/11) – ASIC Project Cost, ASIC Design Flow
• Lecture 3 (8/25/11) – Introduction to VHDL for synthesis
• Lecture 4 (8/30/11) – VHDL: Combinational Models, Sequential Models, Modelsim
• Lecture 5 (9/1/11) – Above continued. My .bashrc file (put in your home directory and name it .bashrc)
• Lecture 6 (9/6/11) – Above Sequential Models, VHDL Testbenches
• Lecture 7 (9/8/11) – VHDL Finite State Machines, Multiplier Example(Nelson)
• Lecture 8 (9/13/11) – VHDL Example: Multiplier Example(Smith)
• Lecture 9 (9/15/11) – Synthesis with LeonardoSpectrum
• Lecture 10 (9/17/11) – Timing Analysis, Synthesis with LeonardoSpectrum
• Lecture 11 (9/20/11) – Synthesis with LeonardoSpectrum
• Lecture 12 (9/22/11) – Divider synthesis example, VITAL models and SDF files
• Lecture 13 (9/27/11) – VITAL/SDF simulation example, Synopsys Design Compiler
• Lecture 14 (9/29/11) – ASIC CMOS Physical Design
• Lecture 15 (10/4/11) – ASIC CMOS Physical Design (continued)
• ASIC CAD Seminar (10/5/11) – for VLSI Design & Test Seminar
• MIDTERM EXAM (Thursday, 10/6/11)
• Lecture 16 (10/11/11) – Exam/project review, ASIC Standard Cell Design Flow
• Lecture 17 (10/13/11) – FPGA Design (Prof. Stroud)
• Lecture 18 (10/18/11) - ASIC Standard Cell Design Flow (continued)
• Lecture 19 (10/20/11) - ASIC Standard Cell Design Flow – Post-Layout DRC, LVS, PEX
• Lecture 20 (10/27/11) – PEX (continued), ASIC top-level design
• Lecture 21 (11/1/11) – Top-level design (continued), Post-layout simulation
• Lecture 22 (11/3/11) – Post-layout simulation
• Lecture 23 (11/8/11) – Post-layout simulation
• Lecture 24 (11/10/11) – Testing tools and ATPG
• Lecture 25 (11/15/11) - Tessent FastScan, ATPG, Fault Simulation
• Lecture 26 (11/17/11) – Tessent DFTAdvisor, Design for Testablity
• Lecture 27 (11/29/11) – Boundary Scan Design, Tessent BSDAdvisor
• Lecture 28 (21/1/11) – Built-In Self Test (BIST), Tessent LBISTAdvisor, MBISTAdvisor

Homework Assignments:

• Tuesday, August 23: Two-page report on a commercial ASIC (function, technology, characteristics, CAD tools used, etc.)
• Thursday, August 25: Modulo-6 counter (gate level review)
• Thursday, September 1: Modulo-6 counter behavioral and structural models
• Links to: adk.vhd (std. cell models) adk_comp.vhd (pkg of cell component declarations)
• Tuesday, September 6: Simulation of Modulo-6 counter models – Part 1
• Thursday, September 8: Simulation of Modulo-6 counter models – Part 2
• Thursday, September 15: Draft version of Divider model (will be critiqued but not be graded)
• Thursday, September 22: Final Divider model plus simulation.
• Thursday, September 29: Synthesized modulo 6 counter and divider
• Tuesday, October 4: Timing analysis and simulations
• Tuesday, October 18: Option 1: Synopsys DC synthesis and simulation
• Option 2: FPGA implementation and simulation (Link to ELEC4200 page below)
• Synopsys Files: .synopsys_dc_setup.txt file, Sample script, Sample .bashrc file
• Thursday, October 27: Physical layout of standard-cell based circuit
• Friday, November 4 (11 am): Physical layout of chip, including pads
• Friday, November 11 (11 am): Post-layout simulation with ADiT
• FINAL EXAM PROJECTS: (Due Friday, December 2, 4 p.m.)
• ELEC 5250
• ELEC 6250

Useful CAD Tool Links:

• Auburn ECE "Computing Tools" Resources
• Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools
• To access Mentor Graphics IC Flow documentation on a UNIX system, enter the command:  mgcdocs _bk_icflow.pdf
• Mentor Graphics Tools Seminar

· AU Student-Authored Tutorials on Mentor Graphics Tools, ASIC Design Kit (ADK) Standard Cells, Scan-Based Design-for-Test

· Haihua Yan/Gefu Xu

· Ayoush Dixit/Harshit Poladia

• Santa Clara University – VLSI CAD Tutorials for Mentor Graphics
• Virginia Commonwealth University Mentor Graphics EDA Tool Tutorials
• North Carolina State (T. R. Harris) Design Architect Tutorials (buses and hierarchy)
• Documentation on TSMC 0.35um Pads (Tanner Consulting and Engineering Services)
• chiptalk.org – IC Design and EDA Tools Resources
• Modelsim PE Student Edition Download: http://www.model.com/resources/student_edition/download.asp
• Virginia Tech “VLSI Design World” (Cell Libraries, CAD Tool Tutorials)
• North Carolina State University – EDA Wiki (NCSU Cadence Design Kit – CDK & Tutorials)
• Best of the Web – Electronic Design Automation Links

VHDL Links

• VHDL Overview (ELEC 5200/6200)
• Professor Stroud's ELEC 4200 VHDL Resources
• EDA Industry Working Groups for VHDL, Verilog, and related standards
• Hamburg VHDL Archive (Good source of VHDL documentation, models & tools)
• A comparison of VHDL andVerilog with examples of equivalent models in each language
• A comprehensive set of overviews of VHDL, Verilog, System C, PERL, and TCL/TK
• VHDL Cookbook - a 111 page PDF pre-publihed version of The Designer's Guide to VHDL
• A VHDL tutorial (by Weijun Zhang, U.C. Riverside) with good examples and links to reference and related material