Doctoral, Master's and Honors Theses Supervised (Click on name for present email address):

Jins D. Alexander, MS, Auburn, December 2008, Simulation Based Power Estimation for Digital CMOS Technologies
Hillary Grimes, MS, Auburn, August 2008, Reconvergent Fanout Analysis of Bounded Gate Delay Faults, Defense
Fan Wang, MS, Auburn, May 2008, Soft Error Rate Determination for Nanometer CMOS VLSI Circuits, Defense
Christopher Rose, BS Honors, Auburn, June 2007, Active Voice Control: An Implementation of Active Noise Control for Canceling Speech
Nitin Yogi, PhD, Auburn, Spring 2008, Gate-Level Test Generation Using Spectral Methods at Register-Transfer Level, Proposal
Yuanlin Lu, PhD, Auburn, August 2007, Power and Performance Optimization of Static CMOS Circuits with Process Variation, Defense
Kalyana R. Kantipudi, MS, Auburn, May 2007, Minimizing N-Detect Tests for Combinational Circuits, Defense
Alok S. Doshi, MS, Auburn, May 2006, Independence Fault Collapsing and Concurrent Test Generation, Defense
Fei Hu, PhD, Auburn, May 2006, Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits, Defense
Anand Mudlapur, MS, Auburn, May 2006, Practically Realizing Random Access Scan, Defense
Subhashis Majumder, PhD, Jadavpur University, October 2005, Studies in Layout-driven Routing, Thermal Problems and Delay Fault Classification for VLSI Physical Design
Raja K. K. R. Sandireddy, MS, Auburn, May 2005, Hierarchical Fault Collapsing for Logic Circuits, Defense
Siri Uppalapati, MS, Rutgers, October 2004, Low Power Design of Standard Cell Digital VLSI Circuits, Defense
Tezaswi Raja, PhD, Rutgers, May 2004, Minimum Dynamic Power CMOS Design with Variable Input Delay Logic, Defense
Kunal K. Dave, MS, Rutgers, May 2004, Using Contrapositive Rule to Enhance the Implication Graphs of Logic Circuits, Defense
Siri Uppalapati, MS, Rutgers, May 2004, Low Power Design of Standard Cell Digital VLSI Circuits, Defense
Vishal J. Mehta, MS, Rutgers, May 2003, Redundancy Identification in Logic Circuits using Extended Implication Graph and Stem Unobservability Theorems
Lan Rao, PhD, Rutgers, 2003, Graphical CMOS IDDQ Testing Signatures Based on Data Mining.
Yong C. Kim, PhD, Wisconsin, 2002, Combinational Test Generation for Sequential Circuits.
Tezaswi Raja, MS, Rutgers, March 2002, A Reduced Constraint Set Linear Program for Low-Power Design of Digital Circuit
Vivek Gaur, MS, Rutgers, January 2002, A New Transitive Closure Algorithm to Identify Redundancies in Logic Circuits.
Pradip A. Thaker, PhD, GWU, May 2000, Register-Transfer Level Fault Modeling and Test Evaluation Technique for VLSI Circuits
Carlos G. Parodi, MS, Rutgers, January 1999, Exact Non-Enumerative Path-Delay Fault Simulation of Sequential Circuits.
Keerthi Heragu, PhD, Illinois, November 1997, New Techniques to Verify Timing Correctness of Integrated Circuits.
Ananta K. Majhi, PhD, IISc, 1996, Algorithms for Test Generation and Fault Simulation of Path-Delay Faults in Logic Circuits
Marwan A. Gharaybeh, PhD, Rutgers, October 1996, Testing for Timing Correctness of High-Speed VLSI Circuits.
Qing Lin, MS, Rutgers, 1996, Efficient Techniques for a Transitive-Closure Based Test Generation Algorithm.
Soumitra Bose, PhD, CMU, December 1995, Testing for Path Delay Faults in Synchronous Sequential Circuits.
James Sienicki, PhD, Rutgers, October 1995, Super-Linear Speedup in Distributed Test Generation Algorithms.
Keerthi Heragu, MS, Rutgers, May 1994, Approximate and Statistical Methods to Compute Delay Fault Coverage.
Srinivas Komar, PhD, IISc, 1994
Suman Kanjilal, PhD, Rutgers, 1994, Synthesis for Testability Using Test Functions.
Tapan J. Chakraborty, PhD, Rutgers, October 1993, Delay Fault Test-Pattern Generation for Random Logic State Machines.
D. V. Das, PhD, Nebraska, 1992
Srimat T. Chakradhar, PhD, Rutgers, May 1990, Neural Network Models for Test-Pattern Generation.
Hassan A. Farhat, PhD, Nebraska, 1988
Kwang-Ting (Tim) Cheng, PhD, UC-Berkeley, 1988, A Simulation-Based Directed-Search Method for Test Vector Generation.

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