Recent Talks and Papers of Vishwani D. Agrawal

My talks:
RFIC Course at PragaTI, July 18, 21, 22, 2008
VLSI D&T Seminar (Fall'07), Effectiveness Measures for VLSI Testing: Defective Parts per Million, Defect Coverage and Fault Coverage
VLSI D&T Seminar (Fall'07), Using Hierarchy in Design Automation: The Fault Collapsing Problem (VDAT'07)
VLSI D&T Seminar (Spring'07), Delay Test Quality Evaluation using Bounded Gate Delays (VTS'07)
VLSI D&T Seminar (Fall'06), Upper Bounding Fault Coverage in Stafan (VTS'06)
VLSI D&T Seminar (Spring'06), Multi-Core Parallelism for Low-Power Design
Talk at Texas Instr., Bangalore, Dec. 29, 2005, Concurrent Test Generation
VLSI D&T Seminar: Implication Graphs (Spring'05), Spectral Testing (Fall'04)
Distinguished Lecture Series (2005), Rutgers University, Talk Abstract slides

ATS'08: Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns, by Yogi and Agrawal
ITC'08: Built-In Self-Calibration of On-Chip DAC and ADC, by Jiang and Agrawal
ISLPED'08: A Tutorial on Test Power, by Agrawal
VDAT'08:
.... Naresh Malipeddi Remembered
.... A Primal-Dual Solution to Minimal Test Generation Problem, by Shukoor and Agrawal slides
.... Tutorial: RFIC Design and Testing for Wireless Communications, by Agrawal and Dai (pdf, 2.5MB) Abstract
NATW'08:
.... Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, by Jiang and Agrawal slides
.... Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation, by Grimes and Agrawal slides
.... Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters, by Wang and Agrawal slides
.... Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns, by Yogi and Agrawal slides
VTS'08: Fault Nodes in Implication Graphs . . . , by Sethuram, Bushnell and Agrawal slides
SSST'08:
.... N-Model Tests for VLSI Circuits, by Yogi and Agrawal slides
.... Soft Error Rate Determination for Nanometer CMOS VLSI Circuits, by Wang and Agrawal slides
VLSI Design'08:
.... Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation, by Lu and Agrawal slides
.... Single Event Upset: An Embedded Tutorial, by Wang and Agrawal slides
ITC'07:
.... Fault Simulation With Bounded Gate Delay Model, by Bose, Grimes and Agrawal slides
.... Estimating Stuck Fault Coverage in Sequential Logic Using State Traversal and Entropy Analysis, by Bose and Agrawal slides
.... SPARTAN: A Spectral and Information Theoretic Approach to Partial Scan, by Khan, Bushnell, Devanathan and Agrawal
T-VLSI, vol. 15, no. 11, pp. 1245-1255, Nov. 2007, Graphical IDDQ Signatures Reduce Defect Level and Yield Loss, by Rao, Bushnell and Agrawal
VDAT'07: Using Hierarchy in Design Automation: The Fault Collapsing Problem, by Sandireddy and Agrawal slides
NATW'07: Optimizing Tests for Multiple Fault Models, by Yogi and Agrawal slides
VTS'07: Delay Test Quality Evaluation using Bounded Gate Delays, by Bose and Agrawal slides
SSST'07: Transition Delay Fault Testing of Microprocessors by Spectral Method, by Yogi and Agrawal slides
VLSI Design'07:
.... A Reduced Complexity Algorithm for Minimizing N-Detect Tests, by Kantipudi and Agrawal slides
.... Statistical Leakage and Timing Optimization for Submicron Process Variation, by Lu and Agrawal slides
.... Spectral RTL Test Generation for Microprocessors, by Yogi and Agrawal slides
JOLPE, vol. 2, no. 3, Dec 2006, CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff, by Lu and Agrawal
ATS'06, Spectral RTL Test Generation for Gate-Level Stuck-at Faults, by Yogi and Agrawal slides
ITC'06, Fault Coverage Estimation for Non-Random Functional Input Sequences, by Bose and Agrawal slides
ISLPED'06, Input-Specific Dynamic Power Optimization for VLSI Circuits, by Hu and Agrawal slides
VDAT'06:
.... Tutorial: Low-Power Electronics and Systems, by Agrawal (118 slides)
.... Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests, by Yogi and Agrawal slides
NATW'06, High-Level Test Generation for Gate-Level Fault Coverage, by Yogi and Agrawal slides
JOLPE, vol. 2, no. 1, Apr 2006, Transistor Sizing of Logic Gates to Maximize Input Delay Variability, by Raja, Agrawal and Bushnell
IEEE-TVLSI, submitted, Variable Input Delay CMOS Logic for Low Power Design, by Raja, Agrawal and Bushnell
VTS'06: Upper Bounding Fault Coverage . . . , by Agrawal, Bose and Gangaram slides
VLSI Design'06: On the Size and Generation of Minimal N-Detection Tests, by Kantipudi and Agrawal slides
ATS05: Concurrent Test Generation, by Agrawal and Doshi slides
ITC05: A Random Access Scan Architecture . . ., by Mudlapur, Agrawal and Singh slides
ICCD05: Enhanced Dual-Transition Probabilistic Power Estimation . . ., by Hu and Agrawal slides
PATMOS05:
.... Variable Input Delay CMOS Logic . . ., by Raja, Agrawal and Bushnell slides
.... Leakage and Dynamic Glitch Power . . ., by Lu and Agrawal slides
VDAT05:
.... Glitch-Free Design of Low Power ASICs . . ., by Uppalapati, Bushnell and Agrawal slides
.... A Novel Random Access Flip-Flop Design, by Mudlapur, Agrawal and Singh slides
.... Independence Fault Collapsing, by Doshi and Agrawal slides
NATW05: Use of Hierarchy in Fault Collapsing, by Sandireddy and Agrawal slides
GLS-VLSI05: Dual-Transition Glitch Filtering . . . , by Hu and Agrawal (poster)
DATE05: Diagnostic and Detection Fault Collapsing . . . , by Sandireddy and Agrawal slides
Talk on Low-Power Design at TI (1/12/05) and Intel (1/13/05) slides abstract
IEEE-TCAD, vol. 24, no. 6, pp. 948-956, June 2005, with Kim and Saluja:
.... "Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits"
IEEE-TCAD, vol. 22, no. 8, pp. 1104-1113, Aug. 2003, with Thaker and Zaghloul:
.... "A Test Evaluation Technique for VLSI Circuits Using Register-Transfer Level Fault Modeling"
VLSI Design'04 Paper, A Tutorial on the Emerging Nanotechnology Devices, ps pdf ppt
VLSI Design'03 Papers, January 6-8, 2003:
.... Exclusive Test and its Applications to Fault Diagnosis, Paper (pdf), Talk (ppt)
.... New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss, Paper (pdf), Talk (ppt)
ITC'02: Analog Macromodeling of Capacitive Coupling Faults ... pdf
IEEE-Electron Device/Solid-State Bangalore Section Talks, Aug 23, 2002:
.... Minimum Dynamic Power CMOS Circuits, 26 slides (ppt)
.... Fundamentals of Testing and DFT, 85 slides (ppt)
IEEE Bangalore Section Talks, January 16, 2002:
.... Delay Testing of Digital Circuits (15 ppt slides)
.... High-Speed VLSI Testing with Slow Test Equipment (13 ppt slides)
VLSI Design'02 Paper: Multiple Faults: Modeling, Simulation and Test (pdf) .... 18 ppt slides
VLSI Design'02 Tutorial, Electronic Testing for SOC Designers, Jan. 8, 2002: 284 ppt slides*
.... *An abbreviated version of the complete VLSI Testing Course
High-Speed VLSI Testing with Slow Test Equipment, Lab Review, June 5, 2001:
.... 3 ppt slides (summary) .... 14 ppt slides (full talk)
Mixed-Signal Test and DFT, Allentown Meeting, May 17, 2001: 43 ppt slides
ATS00 Keynote: Testing in the Fourth Dimension: Talk astract (text) / Slides (ppt)
VLSI Design'95 Keynote: Science, Technology, and the Indian Society

Selected Research Items of Vishwani D. Agrawal

Polynomial time solvable fault detection problems, FTCS'90 paper by Chakradhar, Agrawal and Bushnell (pdf, 2.6MB)
Entropy-based statistical design verification, FTCS'82 paper by Seth and Agrawal (pdf, 2.8MB)
An Information Theoretic Approach to Digital Fault Testing, Paper in IEEETC (pdf, 5.26MB)
Predict - Probabilistic Controllability and Observability Algorithms: Paper in Integration J. (pdf, 1.5MB)
Still Unpublished: Antitest, Exclusive Test and Concurrent Test with Kewal Saluja
CE Education: Test in VLSI Design Course Report / Cost of Education / Interdisciplinary CE Curriculum
Delay Test: Optimistic Update Theorem (Bose), IMTC'99 paper (pdf), with J. Savir / False Paths astract slides
Fault Collapsing: ITC02 pdf ps ppt / ITC03 pdf ps ppt / VDAT03 doc ppt / DATE05 pdf ppt / MS Thesis ppt
High-Level Testing: Astract (doc) Slides (ppt) / ITC'00 ps pdf / Thaker's Thesis (pdf)
High-Speed Test: VDAT'00 talk powerpoint, with C. G. Parodi
Low-Power Design: Talk astract (text) / Slides (ppt) / Paper 1 ps pdf / Paper 2 ps pdf / Paper 3 ps pdf ppt
. . . Paper 4 ps pdf ppt / Paper 5 pdf (unpublished) / Raja's Theses, MS pdf, PhD pdf ppt / Siri's MS Thesis pdf ppt
. . . Paper 6 pdf ppt / FeiHu's PhD Thesis Defense
Redundancy Identification: ATS'96 ps pdf / My talk ppt / DELTA'02 ps ppt / VLSI Design'03 pdf ppt
. . . NATW'03 pdf ppt / Manuscript pdf / NATW'04 pdf / Dave's MS Thesis / VLSI Design'05 pdf ppt
Spectral Methods in Testing: DATE'01 ps pdf, with Michael Hsiao
. . .VTS'01 paper / ATS'00 paper (doc) / VLSI Design'02 Tutorial (ppt) / ITC'04 paper
Test Generation: VLSI Design'01 paper ps pdf ppt, ITC'01 paper ps pdf, with Y. Kim and K. Saluja
Verification: AT&T Test Conf.'95 / VLSI Design'96 / VLSI Design'00 Paper ps pdf
VLSI Test Quality and Coverage: DATE'00 ps pdf / ITSW'01 ppt / NATW'01 pdf, with Jose T. de Sousa
See Bibliography, 1968-1980 for Early Work on Antennas & Microwaves
or the Full Bibliography

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