%% Agrawal V
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@article{Jain66,
   author = {V. K. Jain and V. D. Agrawal},
   title = {Directional Loudspeaker System for a Big Hall},
   journal = {J.I.T.E. (India)},
   volume = {12},
   pages = {29--35},
   month = jan,
   year = {1966}
}

@article{Chatterjee68,
   author = {S. K. Chatterjee and V. D. Agrawal and R. Chatterjee},
   title = {Reactance Modulated Dielectric Rod Waveguide},
   journal = {J.I.E. (India)},
   volume = {43, Part ET2},
   pages = {103--114},
   year = {1968}
}

@article{Lo68,
   author = {Y. T. Lo and V. D. Agrawal},
   title = {Removal of Blindness in Phased Arrays},
   journal = {Proc. IEEE},
   volume = {56},
   pages  = {1586--1588},
   month = sep,
   year = {1968}
}

@article{Agrawal69,
   author = {V. D. Agrawal and Y. T. Lo},
   title = {Distribution of Sidelobe Level in Random Arrays},
   journal = {Proc. IEEE},
   volume = {57},
   pages = {1764--1765},
   month = oct,
   year = {1969}
}

@inproceedings{Lo70,
   author = {Y. T. Lo and V. D. Agrawal and A. R. Panicali},
   title = {A Review of the Theory of Random Arrays with Some Recent Results},
   booktitle = {Proc. 4th Colloquium on Microwave Communication},
   address = {Budapest, Hungary},
   month = apr,
   year = {1970}
}

@techreport{Agrawal72,
   author = {V. D. Agrawal and D. R. Barkhurst},
   title = {Vertically Polarized Dipole Evaluation -- {F}inal Report},
   institution= {EG\&G, Inc.},
   address = {Albuquerque, New Mexico},
   number = {AL-685},
   month = {March 1,},
   year = {1972}
}

@article{Agrawal72a,
   author = {V. D. Agrawal and Y. T. Lo},
   title = {Mutual Coupling in Phased Arrays of Randomly Spaced Antennas},
   journal = {IEEE Trans. Antennas and Propagation},
   volume = {AP-20},
   month = {May},
   year  = {1972},
   pages = {288--295},
   note = {Also Antenna Lab. Report No. 71-1, University of Illinois, Urbana, Illinois}
}

@article{Agrawal72b,
   author = {V. D. Agrawal and Y. T. Lo},
   title = {Anomalies of Dielectric Coated Gratings},
   journal = {Applied Optics},
   volume = {11},
   pages = {1946--1951},
   month = sep,
   year = {1972}
}

@article{Agrawal72c,
   author = {V. D. Agrawal and P. Agrawal},
   title = {An Automatic Test Generation System for {I}lliac {IV} Logic Boards},
   journal = {IEEE Trans. Comput.},
   volume = {C-21},
   pages = {1015--1017},
   month = sep,
   year = {1972}
}

@inproceedings{Agrawal73,
   author = {V. D. Agrawal},
   title = {A Novel Technique of Electronic Scanning},
   booktitle = {Proc. Symposium on Sonar Systems and Ultrasonics},
   organization = {Indian Institute of Technology, New Delhi},
   month = {May 3-5,},
   year = {1973}
}

@article{Agrawal74,
   author = {V. D. Agrawal and R. K. Arora},
   title = {Scanning Transients in Phased Array Antennas},
   journal = {Proc. IEEE},
   volume = {62},
   pages = {850--851},
   month = jun,
   year = {1974}
}

@article{Arora74,
   author = {R. K. Arora and V. D. Agrawal},
   title = {Frequency-Spread Associated with Fast Electronic Scanning},
   journal = {Proc. IEEE},
   volume = {62},
   pages = {1175--1176},
   month = aug,
   year = {1974}
}

@article{Agrawal74a,
   author = {V. D. Agrawal},
   title = {Comments on Beamwidth of Phased Arrays},
   journal = {IEEE Trans. Ant. Prop.},
   volume = {AP-22},
   pages = {841--842},
   month = nov,
   year = {1974}
}

@techreport{Shahani75,
   author = {D. T. Shahani and V. D. Agrawal},
   title = {An Experimental Phased Array Antenna},
   institution = {School of Radar Studies, Indian Institute of Technology},
   number = {SRS-75-1},
   address = {New Delhi},
   month = jan,
   year = {1975}
}

@inproceedings{Agrawal75,
   author = {P. Agrawal and V. D. Agrawal},
   title = {On Improving the Efficiency of Monte Carlo Test Generation},
   booktitle = {Digest of Fifth Int. Fault Tolerant Computing Symposium},
   pages = {205--209},
   address = {Paris, France},
   month = {June 18-20,},
   year = {1975}
}

@article{Agrawal75a,
   author = {P. Agrawal and V. D. Agrawal},
   title = {Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Networks},
   journal = {IEEE Trans. Comput.},
   volume = {C-24},
   pages = {691--695},
   month = jul,
   year = {1975}
}

@article{Agrawal76,
   author = {P. Agrawal and V. D. Agrawal},
   title = {On Monte Carlo Testing of Logic Tree Networks},
   journal = {IEEE Trans. Comput.},
   volume = {C-25},
   pages = {664--667},
   month = jun,
   year = {1976}
}

@techreport{Agrawal76a,
   author = {V. D. Agrawal and W. A. Imbriale},
   title = {Dichroic Subreflector},
   institution = {TRW Defense and Space Systems Group},
   number = {76-7323.A4-72},
   address = {Redondo Beach, California},
   month = sep,
   year = {1976}
}

@inproceedings{Agrawal76b,
   author = {V. D. Agrawal and W. A. Imbriale},
   title = {Experimental and Theoretical Design of Dichroic Surface for a Spacecraft Antenna},
   booktitle = {Proc. IEEE Int. AP-S Symp.},
   address = {Amherst, MA},
   month = oct,
   year = {1976},
   pages = {105--108}
}

@inproceedings{Agrawal77,
   author = {V. D. Agrawal and W. A. Imbriale},
   title = {Analysis of Frequency Selective Surfaces Printed on Dielectric Sheet},
   booktitle = {Proc. IEEE Int. AP-S Symp.},
   address = {Palo Alto, CA},
   month = jun,
   year = {1977}
}

@techreport{Agrawal77a,
   author = {V. D. Agrawal and G. G. Wong},
   title = {Helix Antenna for Multiple Access Array of {TDRSS} Spacecraft},
   institution = {TRW Defense and Space Systems Group},
   number = {TDRSS-77-331-107},
   address = {Redondo Beach, California},
   month = dec,
   year = {1977}
}

@article{Agrawal78,
   author = {V. D. Agrawal},
   title = {Grating Lobe Suppression in Phased Arrays by Subarray Rotation},
   journal = {Proc. IEEE},
   volume = {66},
   pages = {347--349},
   month = mar,
   year = {1978}
}

@inproceedings{Agrawal78a,
   author = {V. D. Agrawal and T. C. Tong},
   title = {Grating Lobe Suppression in Multiple Access Array of {TDRSS} Spacecraft},
   booktitle = {IEEE Int. AP-S Symp. Digest},
   pages = {178--181},
   address = {Washington, D.C.},
   month = may,
   year = {1978}
}

@article{Agrawal78b,
   author = {V. D. Agrawal},
   title = {Selection of Element for a Scanned Array Antenna},
   journal = {Archiv fur Elektronik und Ubertragungstechnik (AEU)},
   volume = {32},
   pages = {493--495},
   month = nov,
   year = {1978}
}

@article{Agrawal78c,
   author = {V. D. Agrawal},
   title = {When to Use Random Testing},
   journal = {IEEE Trans. Comput.},
   volume = {C-27},
   pages = {1054--1055},
   month = nov,
   year = {1978}
}

@article{Agrawal79,
   author = {V. D. Agrawal},
   title = {Electrostatic Analog for Finding Nonintersecting Paths},
   journal = {IETE Student's Journal (India)},
   volume = {20},
   pages = {3--7},
   month = jan,
   year = {1979}
}

@inproceedings{Agrawal79a,
   author = {V. D. Agrawal and G. G. Wong},
   title = {A High Performance Helical Element for Multiple Access Array on {TDRSS} Spacecraft},
   booktitle = {IEEE Int. AP-S Symp. Digest},
   pages = {481--484},
   address = {Seattle, Washington},
   month = jun,
   year = {1979}
}

@article{Agrawal79b,
   author = {V. D. Agrawal and W. A. Imbriale},
   title = {Design of a Dichroic Cassegrain Subreflector},
   journal = {IEEE Trans. Ant. Prop.},
   volume = {AP-27},
   pages = {466--473},
   month = jul,
   year = {1979}
}

@article{Agrawal79c,
   author = {V. D. Agrawal},
   title = {Authors Reply to Comments on When to Use Random Testing},
   journal = {IEEE Trans. Comput.},
   volume = {C-28},
   pages = {581},
   month = aug,
   year = {1979}
}

@article{Agrawal79d,
   author = {V. D. Agrawal},
   title = {Comments on An Approach to Highly Integrated, Computer Maintained Cellular Arrays},
   journal = {IEEE Trans. Comput.},
   volume = {C-28},
   pages = {691--693},
   month = sep,
   year = {1979}
}

@inproceedings{Agrawal80,
   author = {V. D. Agrawal and A. K. Bose and P. Kozak and H. N. Nham and E. Pacas-Skewes},
   title = {A Mixed-Mode Simulator},
   booktitle = {Proc. 17th Des. Auto. Conf.},
   pages = {618--625},
   address = {Minneapolis, Minnesota},
   month = {June 23-25,},
   year = {1980}
}

@inproceedings{Agrawal80a,
   author = {V. D. Agrawal},
   title = {Information Theory in Digital Testing -- {A} New Approach to Functional Test Pattern Generation},
   booktitle = {Proc. Int. Conf. Cir. Comput.},
   pages = {928--931},
   address = {Port Chester, N.Y.},
   month = {October 1-3,},
   year = {1980}
}

@inproceedings{Agrawal80b,
   author = {V. D. Agrawal},
   title = {Random Test Generation -- {A} Tutorial},
   booktitle = {Proc. Bell Syst. Conf. on Electronic Testing},
   pages = {9--11},
   address = {Princeton, N.J.},
   month = {October 14-16,},
   year = {1980}
}

@article{Agrawal80c,
   author = {V. D. Agrawal and Y. T. Lo},
   title = {Comments on Characterization of the Random Array Peak Sidelobes},
   journal = {IEEE Trans. Ant. Prop.},
   volume = {AP-28},
   pages = {946--948},
   month = nov,
   year = {1980}
}

@inproceedings{Agrawal81,
   author = {V. D. Agrawal and S. C. Seth and P. Agrawal},
   title = {{LSI} Product Quality and Fault Coverage},
   booktitle = {Proc. 18th Des. Auto. Conf.},
   pages = {196--203},
   address = {Nashville, TN},
   month = {June 29-July 1,},
   year = {1981}
}

@article{Agrawal81a,
   author = {V. D. Agrawal},
   title = {An Information Theoretic Approach to Digital Testing},
   journal = {IEEE Trans. Comput.},
   volume = {C-30},
   pages = {582--587},
   month = aug,
   year = {1981}
}

@inproceedings{Mercer81,
   author = {M. R. Mercer and V. D. Agrawal and C. M. Roman},
   title = {An {LSI} Chip Designed for Testability},
   booktitle = {Proc. Bell System Conference on Electronic Testing},
   address = {Princeton, N.J.},
   month = sep,
   year = {1981}
}

@article{Agrawal81b,
   author = {V. D. Agrawal},
   title = {Sampling Techniques for Determining Fault Coverage in {LSI} Circuits},
   journal = {J. Digital Syst.},
   volume = {V},
   pages = {189--202},
   month = {Fall},
   year = {1981}
}

@inproceedings{Agrawal81c,
   author = {V. D. Agrawal},
   title = {Emerging Roles of {VLSI} Testing},
   booktitle = {Proc. SEMICON/Southwest},
   address = {Dallas, Texas},
   month = {October 13-14,},
   year = {1981}
}

@inproceedings{Mercer81a,
   author = {M. R. Mercer and V. D. Agrawal and C. M. Roman},
   title = {Test Generation for Highly Sequential Scan-testable Circuits through Logic Transformation,},
   booktitle = {Proc. International Test Conference},
   address = {Philadelphia, PA},
   month = {October 27-29,},
   year = {1981},
   pages = {561--565}
}

@article{Seth81,
   author = {S. C. Seth and V. D. Agrawal},
   title = {Forecasting Reject Rate of Tested {LSI} Chips},
   journal = {IEEE Electron Device Letters},
   volume = {EDL-2},
   pages = {286--287},
   month = nov,
   year = {1981}
}

@article{Agrawal81d,
   author = {V. D. Agrawal and A. K. Bose and P. Kozak and H. N. Nham and E. Pacas-Skewes},
   title = {Mixed-mode Simulation in the {MOTIS} System},
   journal = {J. Digital Syst.},
   volume = {V},
   pages = {383--400},
   month = {Winter},
   year = {1981}
}

@article{Agrawal82,
   author = {V. D. Agrawal and S. C. Seth and P. Agrawal},
   title = {Fault Coverage Requirements in Production Testing of {LSI} Circuits},
   journal = {IEEE J. Sol. St. Circ.},
   volume = {SC-17},
   pages = {57--61},
   month = feb,
   year = {1982}
}

@inproceedings{Mercer82,
   author = {M. R. Mercer and V. D. Agrawal},
   title = {Testability Strategies for Custom Polycell Designs},
   booktitle = {Computer Elements Workshop},
   address = {New York, N.Y.},
   month = {May 21-22},
   year = {1982}
}

@inproceedings{Agrawal82a,
   author = {V. D. Agrawal},
   title = {Synchronous Path Analysis in {MOS} Circuit Simulator},
   booktitle = {Proc. 19th Des. Auto. Conf.},
   pages = {629--635},
   address = {Las Vegas, Nevada},
   month = {June 14-16,},
   year = {1982}
}

@article{Seth82,
   author = {S. C. Seth and V. D. Agrawal},
   title = {Statistical Design Verification},
   journal = {12th Int. Fault Tolerant Computing Symp.},
   address = {Santa Monica, CA},
   month = {June 22-24,},
   year = {1982},
   note = {Digest of Papers pp. 393-399.}
}

@inproceedings{Mercer82a,
   author = {M. R. Mercer and V. D. Agrawal},
   title = {Applications of Testability Measures in {VLSI} Design},
   booktitle = {Proc. Bell System Conference on Electronic Testing},
   pages = {52--58},
   address = {Princeton, N.J.},
   month = {October 5-7},
   year = {1982}
}

@article{Agrawal82b,
   author = {V. D. Agrawal and M. R. Mercer},
   title = {Testability Measures -- {W}hat Do They Tell Us?},
   journal = {Proc. Int. Test Conf.},
   address = {Philadelphia, PA},
   month = {November 16-18,},
   year = {1982},
   pages = {391--396}
}

@inproceedings{Jain83,
   author = {S. K. Jain and V. D. Agrawal},
   title = {Statistical Fault Analysis -- {A} Technique for Estimating Fault Coverage through Good Circuit Simulation},
   booktitle = {IEEE Design for Testability Workshop},
   address = {Vail, CO},
   month = {April 12-14},
   year = {1983}
}

@inproceedings{Jain83a,
   author = {S. K. Jain and V. D. Agrawal},
   title = {Test Generation for {MOS} Circuits using {D}-Algorithm},
   booktitle = {Proc. 20th Des. Auto. Conf.},
   pages = {64--70},
   address = {Miami Beach, Florida},
   month = jun,
   year = {1983}
}

@inproceedings{Agrawal83,
   author = {V. D. Agrawal and S. K. Jain and D. M. Singer},
   title = {Design for Testability -- {T}utorial},
   booktitle = {Proc. Bell Syst. Conf. on Electronic Testing},
   address = {Princeton, N.J.},
   month = oct,
   year = {1983}
}

@inproceedings{Seth82a,
   author = {S. C. Seth and V. D. Agrawal},
   title = {Characterizing the {LSI} Yield Equation from Chip Test Data},
   booktitle = {Proc. Int. Conf. Circ. Comp.},
   pages = {556--559},
   address = {New York, N.Y.},
   month = {Sept. 28-Oct. 1,},
   year = {1982},
   note = {Also IEEE Trans. CAD Vol. CAD-3, pp. 123-126, April 1984.}
}

@article{Mercer84,
   author = {M. R. Mercer and V. D. Agrawal},
   title = {A Novel Clocking Technique for {VLSI} Circuit Testability},
   journal = {IEEE J. Sol. St. Circ.},
   volume = {SC-19},
   pages = {207--212},
   month = apr,
   year = {1984}
}

@inproceedings{Jain84,
   author = {S. K. Jain and M. Weisel and V. D. Agrawal},
   title = {Scan Overhead Optimization in Standard Cell Design},
   booktitle = {IEEE Design for Testability Workshop},
   address = {Vail, CO},
   month = {April 24-26},
   year = {1984}
}

@inproceedings{Agrawal84,
   author = {V. D. Agrawal and S. K. Jain and D. M. Singer},
   title = {Automation in Design for Testability},
   booktitle = {Custom Integrated Circuits Conf.},
   pages = {159--163},
   address = {Rochester, N.Y.},
   month = {May 21-23,},
   year = {1984}
}

@inproceedings{Reddy84,
   author = {S. M. Reddy and M. K. Reddy and V. D. Agrawal},
   title = {Robust Tests for Stuck-open Faults in {CMOS} Combinational Logic Circuits},
   booktitle = {Proc. 14th Int. Fault Tolerant Comp. Symp.},
   pages = {44--49},
   address = {Kissimmee, Florida},
   month = {June 20-22,},
   year = {1984}
}

@inproceedings{Jain84a,
   author = {S. K. Jain and V. D. Agrawal},
   title = {{STAFAN}: An Alternative to Fault Simulation},
   booktitle = {Proc. ACM IEEE 21st Des. Auto. Conf.},
   pages = {18--23},
   address = {Albuquerque, N.M.},
   month = {June 25-27,},
   year = {1984}
}

@inproceedings{Dunlop84,
   author = {A. E. Dunlop and V. D. Agrawal and D. N. Deutsch and M. F. Jukl and P. Kozak and M. Wiesel},
   title = {Chip Layout Optimization using Critical Path Weighting},
   booktitle = {Proc. ACM IEEE 21st Des. Auto. Conf.},
   pages = {133--136},
   address = {Albuquerque, N.M.},
   month = {June 25-27,},
   year = {1984}
}

@inproceedings{Reddy84a,
   author = {S. M. Reddy and V. D. Agrawal and S. K. Jain},
   title = {A Gate Level Model for {CMOS} Combinational Logic Circuits with Application to Fault Detection},
   booktitle = {Proc. ACM IEEE 21st Des. Auto. Conf.},
   pages = {504--509},
   address = {Albuquerque, N.M.},
   month = {June 25-27,},
   year = {1984}
}

@article{Agrawal84a,
   author = {V. D. Agrawal and S. K. Jain and D. M. Singer},
   title = {A {CAD} System for Design for Testability},
   journal = {VLSI Design},
   volume = {V},
   pages = {46--54},
   month = oct,
   year = {1984}
}

@inproceedings{Agrawal84b,
   author = {V. D. Agrawal},
   title = {Will Testability Analysis Replace Fault Simulation - {A} Panel Discussion},
   booktitle = {Proc. Int. Test Conf.},
   address = {Philadelphia, PA},
   month = oct,
   year = {1984}
}

@inproceedings{Agrawal84c,
   author = {V. D. Agrawal},
   title = {Computer-Aids in {VLSI} Design},
   booktitle = {Proc. IEEE Int. Conf. on Computers, Systems and Signal Processing},
   address = {Bangalore, India},
   month = {December 10-12,},
   year = {1984}
}

@article{Jain85,
   author = {S. K. Jain and V. D. Agrawal},
   title = {Statistical Fault Analysis},
   journal = {IEEE Design \& Test of Computers},
   volume = {2},
   pages = {38--44},
   month = feb,
   year = {1985}
}

@inproceedings{Agrawal85,
   author = {V. D. Agrawal and S. H. C. Poon},
   title = {{VLSI} Design Process},
   booktitle = {Proc. ACM Computer Science Conference},
   pages = {74--78},
   address = {New Orleans, Louisiana},
   month = {March 12-14,},
   year = {1985}
}

@article{Seth85,
   author = {S. C. Seth and V. D. Agrawal},
   title = {Cutting Chip Testing Costs},
   journal = {IEEE Spectrum},
   volume = {22},
   pages = {38--45},
   month = apr,
   year = {1985}
}

@article{Jain85a,
   author = {S. K. Jain and V. D. Agrawal},
   title = {Modeling and Test Generation Algorithms for {MOS} Circuits},
   journal = {IEEE Trans. Comput.},
   volume = {C-34},
   pages = {426--433},
   month = may,
   year = {1985}
}

@inproceedings{Agrawal85a,
   author = {V. D. Agrawal and S. C. Seth and C. C. Chuang},
   title = {Probabilistically Guided Test Generation},
   booktitle = {Proc. Int. Symp. on Circuits and Systems},
   pages = {687--690},
   address = {Kyoto, Japan},
   month = jun,
   year = {1985}
}

@inproceedings{Seth85a,
   author = {S. C. Seth and L. Pan and V. D. Agrawal},
   title = {{PREDICT} - Probabilistic Estimation of Digital Circuit Testability},
   booktitle = {Proc. Fault Tolerant Computing Symposium},
   pages = {220--225},
   address = {Ann Arbor, Michigan},
   month = {June 19-21,},
   year = {1985}
}

@inproceedings{Agrawal85b,
   author = {P. Agrawal and V. D. Agrawal and N. N. Biswas},
   title = {Multiple Output Minimization},
   booktitle = {Proc. 22nd Design Automation Conference},
   pages = {674--680},
   address = {Las Vegas, Nevada},
   month = {June 24-26,},
   year = {1985}
}

@article{Jain85b,
   author = {S. K. Jain and V. D. Agrawal},
   title = {Clarifying Statistical Fault Analysis -- {A}uthors' Reply},
   journal = {IEEE Design \& Test of Computers},
   volume = {2},
   pages = {7--8},
   month = aug,
   year = {1985}
}

@inproceedings{Agrawal85c,
   author = {V. D. Agrawal and S. C. Seth},
   title = {Probabilistic Testability},
   booktitle = {Proc. Int. Conf. on Computer Design},
   pages = {562--565},
   address = {Port Chester, NY},
   month = oct,
   year = {1985}
}

@inproceedings{Agrawal85d,
   author = {V. D. Agrawal},
   title = {Stafan Takes a Middle Course (Position Statement)},
   booktitle = {Proc. International Test Conference},
   address = {Philadelphia, PA},
   month = nov,
   year = {1985}
}

@article{Seth85b,
   author = {S. C. Seth and V. D. Agrawal},
   title = {A Review of Testing of {VLSI} Devices},
   journal = {IETE Tech. Review},
   volume = {1},
   pages = {363--374},
   month = nov,
   year = {1985}
}

@inproceedings{Agrawal85e,
   author = {V. D. Agrawal},
   title = {{VLSI} Testing},
   booktitle = {Proc. First International Workshop on VLSI Design},
   address = {Madras, India},
   month = {December 18-26},
   year = {1985}
}

@inproceedings{Seth86,
   author = {S. C. Seth and B. B. Bhattacharya and V. D. Agrawal},
   title = {An Exact Analysis for Efficient Computation of Random-Pattern Testability in Combinational Circuits},
   booktitle = {Proc. Fault Tolerant Computing Symposium},
   pages = {318--323},
   address = {Vienna, Austria},
   month = {July 1-3,},
   year = {1986}
}

@inproceedings{Lin86,
   author = {T. Lin and V. D. Agrawal},
   title = {A Test Generator for Scan-Design {VLSI} Circuits},
   booktitle = {Proc. AT\&T Conference on Electronic Testing},
   pages = {23.1--23.7},
   address = {Jamesburg, NJ},
   month = sep,
   year = {1986}
}

@inproceedings{Agrawal86,
   author = {V. D. Agrawal and D. D. Johnson},
   title = {Logic Modeling of {PLA} Faults},
   booktitle = {Proc. Int. Conf. on Computer Design},
   pages = {86--88},
   address = {Port Chester, NY},
   month = oct,
   year = {1986}
}

@inproceedings{Srinivas86,
   author = {N. C. E. Srinivas and V. D. Agrawal},
   title = {{PROVE}: Prolog Based Verifier},
   booktitle = {Proc. Int. Conf. on Computer-Aided Design},
   pages = {306--309},
   address = {Santa Clara, CA},
   month = nov,
   year = {1986}
}

@inproceedings{Agrawal87,
   author = {V. D. Agrawal and K. T. Cheng and D. D. Johnson and T. Lin},
   title = {A Complete Solution to the Partial Scan Problem},
   booktitle = {Proc. Int. Test Conference},
   pages = {44--51},
   address = {Washington, D.C.},
   month = sep,
   year = {1987}
}

@inproceedings{Agrawal87a,
   author = {V. D. Agrawal and K. T. Cheng},
   title = {A Simulation-Based Directed Search Method for Test Generation},
   booktitle = {Proc. Int. Conf. on Computer Design (ICCD)},
   pages = {48--51},
   address = {Port Chester, NY},
   month = oct,
   year = {1987}
}

@inproceedings{Agrawal87b,
   author = {V. D. Agrawal and K. T. Cheng and P. Agrawal},
   title = {Use of a Concurrent Fault Simulator for Test Vector Generation},
   booktitle = {Proc. AT\&T Conf. on Electronic Testing},
   pages = {23--28},
   address = {Princeton, NJ},
   month = oct,
   year = {1987}
}

@article{Srinivas88,
   author = {N. C. E. Srinivas and V. D. Agrawal},
   title = {Formal Verification of Digital Circuits using Hybrid Simulation},
   journal = {Circuits and Devices},
   volume = {4},
   pages = {19--27},
   month = jan,
   year = {1988}
}

@article{Agrawal88,
   author = {V. D. Agrawal and K. T. Cheng and D. D. Johnson and T. Lin},
   title = {Designing Circuits with Partial Scan},
   journal = {IEEE Design \& Test of Computers},
   volume = {5},
   pages = {8--15},
   month = apr,
   year = {1988}
}

@incollection{Agrawal88a,
   author = {V. D. Agrawal},
   editor = {F. Lombardi and M. Sami},
   title = {Statistical Testing},
   booktitle = {Testing and Diagnosis of VLSI and ULSI},
   pages = {33--47},
   publisher = {Kluwer Academic Publishers},
   address = {Dordrecht, The Netherlands},
   year = {1988}
}

@incollection{Agrawal88b,
   author = {V. D. Agrawal and K. T. Cheng},
   editor = {F. Lombardi and M. Sami},
   title = {Threshold-Value Simulation and Test Generation},
   booktitle = {Testing and Diagnosis of VLSI and ULSI},
   pages = {311--323},
   publisher = {Kluwer Academic Publishers},
   address = {Dordrecht, The Netherlands},
   year = {1988}
}

@inproceedings{Agrawal88c,
   author = {V. D. Agrawal and K. T. Cheng and P. Agrawal},
   title = {{CONTEST}: {A} Concurrent Test Generator for Sequential Circuits},
   booktitle = {Proc. Des. Auto. Conf.},
   pages = {84--89},
   address = {Anaheim, CA},
   month = jun,
   year = {1988}
}

@inproceedings{Cheng88,
   author = {K. T. Cheng and V. D. Agrawal and E. S. Kuh},
   title = {A Sequential Circuit Test Generator Using Threshold-Value Simulation},
   booktitle = {Digest of Papers, Fault-Tolerant Computing Symposium (FTCS-18)},
   pages = {24--29},
   address = {Tokyo, Japan},
   month = jun,
   year = {1988}
}

@book{Agrawal88d,
   author = {V. D. Agrawal and S. C. Seth},
   title = {Test Generation for {VLSI} Chips},
   publisher = {IEEE Computer Society Press},
   address = {Los Alamitos, CA},
   year = {1988}
}

@inproceedings{Agrawal88e,
   author = {V. D. Agrawal and H. Farhat and S. C. Seth},
   title = {Test Generation by Fault Sampling},
   booktitle = {Proc. Int. Conf. on Computer Design (ICCD-88)},
   pages = {58--61},
   address = {Rye Brook, NY},
   month = oct,
   year = {1988}
}

@inproceedings{Agrawal88f,
   author = {V. D. Agrawal},
   title = {Testability and Productivity - The Merging of the Two Goals},
   booktitle = {Proc. TECHCON'88 (An SRC Conference)},
   pages = {137--140},
   address = {Dallas, TX},
   month = oct,
   year = {1988}
}

@inproceedings{Agrawal88g,
   author = {V. D. Agrawal and S. C. Seth},
   title = {On a Relationship Between Fault Coverage and Circuit Testability},
   booktitle = {Proc. AT\&T Conf. Electronic Testing},
   pages = {16.1--16.6},
   address = {Princeton, NJ},
   month = oct,
   year = {1988}
}

@inproceedings{Agrawal88h,
   author = {P. Agrawal and V. D. Agrawal and K. T. Cheng},
   title = {Fault Simulation in {MARS}},
   booktitle = {Proc. AT\&T Conf. Electronic Testing},
   pages = {40.1--40.9},
   address = {Princeton, NJ},
   month = oct,
   year = {1988}
}

@inproceedings{Chakradhar88,
   author = {S. T. Chakradhar and M. L. Bushnell and V. D. Agrawal},
   title = {Automatic Test Generation Using Neural Networks},
   booktitle = {Proc. Int. Conf. on Computer-Aided Design (ICCAD-88)},
   pages = {416--419},
   address = {Santa Clara, CA},
   month = nov,
   year = {1988}
}

@incollection{Seth89,
   author = {S. C. Seth and V. D. Agrawal},
   editor = {I. Koren},
   title = {On the Probability of Fault Occurrence},
   booktitle = {Defect and Fault Tolerance in VLSI Systems},
   pages = {47--52},
   publisher = {Plenum Publishing Corp.},
   year = {1989}
}

@incollection{Agrawal89,
   author = {V. D. Agrawal and S. M. Reddy},
   editor = {J. DiGiacomo},
   title = {Fault Modeling and Test Generation},
   booktitle = {VLSI Handbook},
   pages = {Chapter 8},
   publisher = {McGraw-Hill},
   address = {New York},
   year = {1989}
}

@article{Agrawal89a,
   author = {V. D. Agrawal},
   title = {Design Automation, Expert Opinion},
   journal = {IEEE Spectrum},
   volume = {26},
   pages = {36--37},
   month = jan,
   year = {1989}
}

@article{Agrawal89b,
   author = {V. D. Agrawal and K. T. Cheng and P. Agrawal},
   title = {A Directed Search Method for Test Generation Using a Concurrent Simulator},
   journal = {IEEE Trans. on Computer-Aided Design},
   volume = {8},
   pages = {131--138},
   month = feb,
   year = {1989}
}

@inproceedings{Seth89a,
   author = {S. C. Seth and V. D. Agrawal and H. Farhat},
   title = {A Theory of Testability with Application to Fault Coverage Analysis},
   booktitle = {Proc. European Test Conference},
   pages = {139--143},
   address = {Paris, France},
   month = apr,
   year = {1989}
}

@article{Seth89b,
   author = {S. C. Seth and V. D. Agrawal},
   title = {A New Model for Computation of Probabilistic Testability in Combinational Circuits},
   journal = {INTEGRATION, The VLSI Journal},
   volume = {7},
   pages = {49--75},
   year = {1989}
}

@inproceedings{Cheng89,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Concurrent Test Generation and Design for Testability},
   booktitle = {Proc. Int. Symp. Circ. Syst. (ISCAS)},
   pages = {1935--1938},
   address = {Portland, Oregon},
   month = may,
   year = {1989}
}

@book{Cheng89a,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Unified Methods for {VLSI} Simulation and Test Generation},
   publisher = {Kluwer Academic Publishers},
   address = {Boston},
   year = {1989}
}

@inproceedings{Cheng89b,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {An Economical Scan Design for Sequential Logic Test Generation},
   booktitle = {Proc. 19th Fault-Tolerant Computing Symposium (FTCS-19)},
   pages = {28--35},
   month = jun,
   year = {1989}
}

@inproceedings{Agrawal89c,
   author = {P. Agrawal and V. D. Agrawal and K. T. Cheng and R. Tutundjian},
   title = {Fault Simulation in a Pipelined Multiprocessor System},
   booktitle = {Proc. Int. Test Conf},
   pages = {727--734},
   address = {Washington, DC},
   month = aug,
   year = {1989}
}

@inproceedings{Cheng89c,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {State Assignment for Initializable Synthesis},
   booktitle = {Proc. Int. Conf. Computer-Aided Design (ICCAD-89)},
   pages = {212--215},
   address = {Santa Clara, CA},
   month = nov,
   year = {1989}
}

@inproceedings{Cheng89d,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Design of Sequential Machines for Efficient Test Generation},
   booktitle = {Proc. Int. Conf. Computer-Aided Design (ICCAD-89)},
   pages = {358--361},
   address = {Santa Clara, CA},
   month = nov,
   year = {1989}
}

@inproceedings{Agrawal90,
   author = {V. D. Agrawal and K. T. Cheng},
   title = {An Architecture for Synthesis of Testable Finite State Machines},
   booktitle = {Proc. First European Design Automation Conference},
   pages = {612--616},
   address = {Glasgow, UK},
   month = mar,
   year = {1990}
}

@article{Cheng90,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {A Partial Scan Method for Sequential Circuits with Feedback},
   journal = {IEEE Trans. Comput.},
   volume = {39},
   pages = {544--548},
   month = apr,
   year = {1990}
}

@article{Seth90,
   author = {S. C. Seth and V. D. Agrawal and H. Farhat},
   title = {A Statistical Theory of Digital Circuit Testability},
   journal = {IEEE Trans. Comput.},
   volume = {39},
   pages = {582--586},
   month = apr,
   year = {1990}
}

@inproceedings{Agrawal90a,
   author = {P. Agrawal and V. D. Agrawal},
   title = {Can Logic Simulators Handle Bidirectionality and Charge Sharing?},
   booktitle = {Proc. Int. Symp. Circ. Syst. (ISCAS)},
   pages = {411--414},
   address = {New Orleans},
   month = may,
   year = {1990}
}

@inproceedings{Cheng90a,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Synthesis of Testable Finite State Machines},
   booktitle = {Proc. Int. Symp. Circ. Syst. (ISCAS)},
   pages = {3114--3117},
   address = {New Orleans},
   month = may,
   year = {1990}
}

@inproceedings{Chakradhar90,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Automatic Test Generation using Quadratic 0-1 Programming},
   booktitle = {Proc. 27th ACM/IEEE Des. Autom. Conf.},
   pages = {654--659},
   address = {Orlando, FL},
   month = jun,
   year = {1990}
}

@inproceedings{Agrawal90b,
   author = {V. D. Agrawal and K. T. Cheng},
   title = {Test Function Specification in Synthesis},
   booktitle = {Proc. 27th ACM/IEEE Des. Autom. Conf.},
   pages = {235--240},
   address = {Orlando, FL},
   month = jun,
   year = {1990}
}

@inproceedings{Cheng90b,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {An Entropy Measure for the Complexity of Multi-Output {B}oolean Functions},
   booktitle = {Proc. 27th ACM/IEEE Des. Autom. Conf.},
   pages = {302--305},
   address = {Orlando, FL},
   month = jun,
   year = {1990}
}

@inproceedings{Chakradhar90a,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Polynomial Time Solvable Fault Detection Problems},
   booktitle = {Proc. 20th Fault-Tolerant Computing Symposium (FTCS-20)},
   pages = {56--63},
   address = {Newcastle-upon-Tyne, UK},
   month = jun,
   year = {1990}
}

@article{Agrawal90c,
   author = {V. D. Agrawal and H. Kato},
   title = {Fault Sampling Revisited},
   journal = {IEEE Design \& Test of Computers},
   volume = {7},
   pages = {32--35},
   month = aug,
   year = {1990}
}

@article{Chakradhar90b,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Toward Massively Parallel Automatic Test Generation},
   journal = {IEEE Trans. CAD},
   volume = {9},
   pages = {981--994},
   month = sep,
   year = {1990}
}

@inproceedings{Das90,
   author = {D. V. Das and S. C. Seth and P. T. Wagner and J. C. Anderson and V. D. Agrawal},
   title = {An Experimental Study on Reject Ratio Prediction for {VLSI} Circuits: Kokomo Revisited},
   booktitle = {Proc. Int. Test Conf.},
   pages = {712--720},
   month = sep,
   year = {1990}
}

@article{Chakradhar90c,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Neural Net and {B}oolean Satisfiability Models of Logic Circuits},
   journal = {IEEE Design \& Test of Computers},
   volume = {7},
   pages = {54--57},
   month = oct,
   year = {1990}
}

@article{Agrawal90d,
   author = {V. D. Agrawal and K. T. Cheng},
   title = {Finite State Machine Synthesis with Embedded Test Function},
   journal = {J. Electronic Testing: Theory and Applications (JETTA)},
   volume = {1},
   number = {3},
   pages = {221--228},
   year = {1990}
}

@inproceedings{Agrawal90e,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Statistical Performance of a Parallel Processing System},
   booktitle = {Proc. ISMM Int. Conf. on Parallel and Distributed Computing and Systems},
   pages = {212--216},
   month = oct,
   year = {1990}
}

@inproceedings{Agrawal90f,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Logic Simulation and Parallel Processing},
   booktitle = {Proc. Int. Conf. on CAD (ICCAD)},
   pages = {496--499},
   month = nov,
   year = {1990}
}

@inproceedings{Agrawal9g,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Performance Estimation in a Massively Parallel System},
   booktitle = {Proc. Supercomputing '90},
   pages = {306--313},
   month = nov,
   year = {1990}
}

@article{Cheng90c,
   author = {K. T. Cheng and V. D. Agrawal and E. S. Kuh},
   title = {A Simulation-Based Method for Generating Tests for Sequential Circuits},
   journal = {IEEE Trans. on Computers},
   volume = {39},
   pages = {1456--1463},
   month = dec,
   year = {1990}
}

@inproceedings{Agrawal91,
   author = {V. D. Agrawal and S. C. Seth and J. S. Deogun},
   title = {Design for Testability and Test Generation with Two Clocks},
   booktitle = {Proc. 4th CSI/IEEE International Symp. on VLSI Design},
   pages = {112--117},
   month = jan,
   year = {1991}
}

@inproceedings{Chakradhar91,
   author = {S. T. Chakradhar and V. D. Agrawal},
   title = {A Novel {VLSI} Solution to a Difficult Graph Problem},
   booktitle = {Proc. 4th CSI/IEEE International Symp. on VLSI Design},
   pages = {124--129},
   month = jan,
   year = {1991}
}

@book{Chakradhar91a,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Neural Models and Algorithms for Digital Testing},
   publisher = {Kluwer Academic Publishers},
   address = {Boston},
   year = {1991}
}

@article{Cheng91,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Methods for Synthesizing Testable Sequential Circuits},
   journal = {AT\&T Technical Journal},
   volume = {70},
   pages = {64--86},
   month = jan,
   year = {1991}
}

@article{Chakradhar91b,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {On Test Generation Using Neural Computers},
   journal = {Intl. J. Computer Aided VLSI Design},
   volume = {3},
   pages = {241--257},
   year = {1991}
}

@article{Cheng91a,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {State Assignment for Testable Design},
   journal = {Int. J. Computer Aided VLSI Design},
   volume = {3},
   pages = {291--307},
   year = {1991}
}

@inproceedings{Bhawmik91,
   author = {S. Bhawmik and C. J. Lin and K. T. Cheng and V. D. Agrawal},
   title = {{PASCANT}: {A} Partial Scan and Test Generation System},
   booktitle = {Proc. Custom Integrated Circ. Conf.},
   month = may,
   year = {1991}
}

@inproceedings{Chakradhar91c,
   author = {S. T. Chakradhar and V. D. Agrawal},
   title = {A Transitive Closure Based Algorithm for Test Generation},
   booktitle = {Proc. 28th Design Automation Conf.},
   month = jun,
   year = {1991}
}

@article{Sardeshmukh91,
   author = {P. C. Sardeshmukh and V. D. Agrawal},
   title = {Filtering of {SEM} Voltage Contrast Images},
   journal = {3rd European Conf. Electron and Optical Beam Testing},
   address = {Como, Italy},
   month = sep,
   year = {1991}
}

@inproceedings{Villoldo91,
   author = {J. Villoldo and P. Agrawal and V. D. Agrawal},
   title = {Stafan Algorithms for {MOS} Circuits},
   booktitle = {Proc. Intl. Conf. Computer Design},
   pages = {56--59},
   month = oct,
   year = {1991}
}

@inproceedings{Agrawal91a,
   author = {V. D. Agrawal},
   title = {Design and Test --- The Two Sides of a Coin},
   booktitle = {Proc. Intl. Conf. Computer Design},
   pages = {12},
   month = oct,
   year = {1991}
}

@inproceedings{Das91,
   author = {D. V. Das and S. C. Seth and V. D. Agrawal},
   title = {Estimating the Quality of Manufactured Digital Sequential Circuits},
   booktitle = {Proc. Intl. Test Conf.},
   pages = {210--217},
   month = oct,
   year = {1991}
}

@inproceedings{Agrawal92,
   author = {P. Agrawal and V. D. Agrawal and S. C. Seth},
   title = {A New Method for Generating Tests for Delay Faults in Non-Scan Circuits},
   booktitle = {Proc. 5th Intl. Conf. VLSI Design},
   pages = {4--11},
   month = jan,
   year = {1992}
}

@inproceedings{Jacob92,
   author = {J. Jacob and V. D. Agrawal},
   title = {Functional Test Generation for Sequential Circuits},
   booktitle = {Proc. 5th Intl. Conf. VLSI Design},
   pages = {17--24},
   month = jan,
   year = {1992}
}

@inproceedings{Agrawal92a,
   author = {V. D. Agrawal},
   title = {Technology Forecast and Weather Prediction (Keynote Address)},
   booktitle = {Proc. 2nd Great Lakes Symp. on VLSI},
   pages = {1--2},
   month = feb,
   year = {1992}
}

@article{Cheng92,
   author = {K. T. Cheng and V. D. Agrawal},
   title = {Initializability Considerations in Sequential Machine Synthesis},
   journal = {IEEE Trans. Comput.},
   volume = {41},
   pages = {374--379},
   month = mar,
   year = {1992}
}

@inproceedings{Chakradhar92,
   author = {S. T. Chakradhar and M. A. Iyer and V. D. Agrawal},
   title = {Energy Minimization Based Delay Testing},
   booktitle = {Proc. European Design Autom. Conf.},
   pages = {280--284},
   month = mar,
   year = {1992}
}

@inproceedings{Chakradhar92a,
   author = {S. T. Chakradhar and S. Kanjilal and V. D. Agrawal},
   title = {A Synthesis for Testability Technique for {PLA}-Based Finite State Machines},
   booktitle = {Proc. European Design Autom. Conf.},
   pages = {361--365},
   month = mar,
   year = {1992}
}

@article{Ulrich92,
   author = {E. Ulrich and K. P. Lentz and J. Arabian and M. Gustin and V. D. Agrawal and P. L. Montessoro},
   title = {The Comparative and Concurrent Simulation of Discrete-Event Experiments},
   journal = {J. Electronic Testing: Theory and Applic. (JETTA)},
   volume = {3},
   pages = {107--118},
   month = may,
   year = {1992}
}

@article{Jacob92a,
   author = {J. Jacob and V. D. Agrawal},
   title = {Multiple Fault Detection in Two-Level Multi-Output Circuits},
   journal = {J. Electronic Testing: Theory and Applic. (JETTA)},
   volume = {3},
   pages = {171--173},
   month = may,
   year = {1992}
}

@inproceedings{Chakraborty92,
   author = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title = {Delay Fault Models and Test Generation for Random Logic Sequential Circuits},
   booktitle = {Proc. Design Autom. Conf.},
   pages = {165--172},
   month = jun,
   year = {1992}
}

@inproceedings{Bhattacharya92,
   author = {D. Bhattacharya and P. Agrawal and V. D. Agrawal},
   title = {Delay Fault Test Generation for Scan/hold Circuits using {B}oolean Expressions},
   booktitle = {Proc. Design Autom. Conf.},
   pages = {159--164},
   month = jun,
   year = {1992}
}

@inproceedings{Chakradhar92b,
   author = {S. T. Chakradhar and S. Kanjilal and V. D. Agrawal},
   title = {Finite State Machine Synthesis with Fault Tolerant Test Function},
   booktitle = {Proc. Design Autom. Conf.},
   pages = {562--567},
   month = jun,
   year = {1992},
   note = {also {\it J. Electronic Testing: Theory and Applic. (JETTA)}, vol. 4, pp. 57-69, February 1993}
}

@inproceedings{Srinivas92,
   author = {M. K. Srinivas and J. Jacob and V. D. Agrawal},
   title = {Finite State Machine Testing Based on Growth and Disappearance Faults},
   booktitle = {Proc. 22nd Fault-Tolerant Comput. Symp.},
   pages = {238--245},
   month = jul,
   year = {1992}
}

@inproceedings{Agrawal92b,
   author = {P. Agrawal and V. D. Agrawal and S. C. Seth},
   title = {{DynaTAPP}: Dynamic Timing Analysis With Partial Path Activation in Sequential Circuits},
   booktitle = {Proc. EURO-DAC},
   pages = {138--141},
   month = sep,
   year = {1992}
}

@article{Agrawal92c,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems},
   journal = {IEEE Trans. Parallel and Distr. Syst.},
   volume = {3},
   pages = {739--746},
   month = nov,
   year = {1992}
}

@inproceedings{Chakraborty92a,
   author = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title = {Path Delay Simulation Algorithms for Sequential Circuits},
   booktitle = {Proc. First Asian Test Symp.},
   pages = {52--56},
   month = nov,
   year = {1992}
}

@inproceedings{Bose93,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {A Path Delay Fault Simulator for Sequential Circuits},
   booktitle = {Proc. 6th International Conf. VLSI Design},
   pages = {269--274},
   month = jan,
   year = {1993}
}

@article{Agrawal93,
   author = {P. Agrawal and V. D. Agrawal and S. C. Seth},
   title = {Generating Tests for Delay Faults in Nonscan Circuits},
   journal = {IEEE Design \& Test of Computers},
   volume = {10},
   pages = {20--28},
   month = mar,
   year = {1993}
}

@article{Agrawal93a,
   author = {V. D. Agrawal and C. R. Kime and K. K. Saluja},
   title = {A Tutorial on Built-In Self-Test, Part 1: Principles},
   journal = {IEEE Design \& Test of Computers},
   volume = {10},
   pages = {73--82},
   month = mar,
   year = {1993}
}

@inproceedings{Einspahr93,
   author = {K. L. Einspahr and S. C. Seth and V. D. Agrawal},
   title = {Clock Partitioning for Testability},
   booktitle = {Proc. 3rd Great Lakes Symp. VLSI},
   pages = {42--46},
   month = mar,
   year = {1993}
}

@inproceedings{Bose93a,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {Delay Fault Testability Evaluation through Timing Simulation},
   booktitle = {Proc. 3rd Great Lakes Symp. VLSI},
   pages = {18--21},
   month = mar,
   year = {1993}
}

@inproceedings{Agrawal93b,
   author = {V. D. Agrawal and T. J. Chakraborty},
   title = {Partial Scan Testing with Single Clock Control},
   booktitle = {Proc. IEEE VLSI Test Symp.},
   pages = {313--315},
   month = apr,
   year = {1993}
}

@inproceedings{Agrawal93c,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Combinational {ATPG} Theorems for Identifying Untestable Faults in Sequential Circuits},
   booktitle = {Proc. European Test Conf.},
   pages = {249--253},
   month = apr,
   year = {1993}
}

@inproceedings{Agrawal93d,
   author = {V. D. Agrawal},
   title = {A Tale of Two Designs: the Cheapest and the Most Economic (Keynote Talk)},
   booktitle = {Second International Workshop on the Economics of Design, Test and Manufacturing},
   month = may,
   year = {1993},
   note = {Also Proc. 12th AT\&T Conference on Electronic Testing, September 1993, pp. 241-244}
}

@article{Chakradhar93,
   author = {S. T. Chakradhar and V. D. Agrawal and S. G. Rothweiler},
   title = {A Transitive Closure Algorithm for Test Generation},
   journal = {IEEE Trans. CAD},
   volume = {12},
   pages = {1015--1028},
   month = jul,
   year = {1993}
}

@article{Agrawal93e,
   author = {V. D. Agrawal and C. R. Kime and K. K. Saluja},
   title = {A Tutorial on Built-In Self-Test, Part 2: Applications},
   journal = {IEEE Design \& Test of Computers},
   volume = {10},
   pages = {69--77},
   month = jun,
   year = {1993}
}

@inproceedings{Agrawal93f,
   author = {P. Agrawal and V. D. Agrawal and J. Villoldo},
   title = {Sequential Circuit Test Generation on a Distributed System},
   booktitle = {Proc. 29th Design Autom. Conf.},
   pages = {107--111},
   month = jun,
   year = {1993}
}

@inproceedings{Chakraborty93,
   author = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title = {Design for Testability for Path Delay Faults in Sequential Circuits},
   booktitle = {Proc. 29th Design Autom. Conf.},
   pages = {453--457},
   month = jun,
   year = {1993}
}

@inproceedings{Agrawal93g,
   author = {P. Agrawal and V. D. Agrawal and J. Villoldo},
   title = {Test Pattern Generation for Sequential Circuits on a Network of Workstations},
   booktitle = {Proc.~2nd International Symp.~High Performance Distr.~Comput.},
   pages = {114--120},
   month = jul,
   year = {1993}
}

@article{Bose93b,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {The Optimistic Update Theorem for Path Delay Testing of Sequential Circuits},
   journal = {J. Electronic Testing: Theory and Applic.},
   volume = {4},
   pages = {285--290},
   month = aug,
   year = {1993}
}

@inproceedings{Kanjilal93,
   author = {S. Kanjilal and S. T. Chakradhar and V. D. Agrawal},
   title = {Test Function Embedding Algorithms with Application to Interconnected Finite State Machines},
   booktitle = {Proc. EURO-DAC},
   pages = {219--224},
   month = sep,
   year = {1993}
}

@inproceedings{Bose93c,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {Logic Systems for Path Delay Test Generation},
   booktitle = {Proc. EURO-DAC},
   pages = {200--205},
   month = sep,
   year = {1993}
}

@inproceedings{Bose93d,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {Generation of Compact Delay Tests by Multiple Path Activation},
   booktitle = {Proc. International Test Conf.},
   pages = {714--723},
   month = oct,
   year = {1993}
}

@inproceedings{Kanjilal93a,
   author = {S. Kanjilal and S. T. Chakradhar and V. D. Agrawal},
   title = {A Synthesis Approach to Design for Testability},
   booktitle = {Proc. International Test Conf.},
   pages = {754--763},
   month = oct,
   year = {1993}
}

@inproceedings{Sureshkumar93,
   author = {P. R. Sureshkumar and J. Jacob and M. K. Srinivas and V. D. Agrawal},
   title = {{FASSAD}: Fault Simulation With Sensitivities and Depth-First Propagation},
   booktitle = {Proc. 2nd Asian Test Symp.},
   pages = {66--71},
   month = nov,
   year = {1993}
}

@article{Bose93e,
   author = {S. Bose and P. Agrawal and V. D. Agrawal},
   title = {Path Delay Fault Simulation of Sequential Circuits},
   journal = {IEEE Trans. VLSI Systems},
   volume = {1},
   pages = {453--461},
   month = dec,
   year = {1993}
}

@article{Das93,
   author = {D.V. Das and S. C. Seth and V. D. Agrawal},
   title = {Accurate Computation of Field Reject Ratio Based on Fault Latency},
   journal = {IEEE Trans. VLSI Systems},
   volume = {1},
   pages = {537--545},
   month = dec,
   year = {1993}
}

@inproceedings{Kanjilal94,
   author = {S. Kanjilal and S. T. Chakradhar and V. D. Agrawal},
   title = {A Test Function Architecture for Interconnected Finite State Machines},
   booktitle = {Proc. 7th International Conference VLSI Design},
   pages = {113--116},
   month = jan,
   year = {1994}
}

@inproceedings{Chou94,
   author = {R.M. Chou and K.K. Saluja and V. D. Agrawal},
   title = {Power Constraint Scheduling of Tests},
   booktitle = {Proc. 7th International Conference VLSI Design},
   pages = {271--274},
   month = jan,
   year = {1994}
}

@inproceedings{Sureshkumar94,
   author = {P. R. Sureshkumar and J. Jacob and M. K. Srinivas and V. D. Agrawal},
   title = {An Improved Deductive Fault Simulator},
   booktitle = {Proc. 7th International Conference VLSI Design},
   pages = {307--310},
   month = jan,
   year = {1994}
}

@book{Ulrich94,
   author = {E. G. Ulrich and V. D. Agrawal and J. H. Arabian},
   title = {Concurrent and Comparative Discrete Event Simulation},
   publisher = {Kluwer Academic Publishers},
   address = {Boston},
   year = {1994}
}

@article{Chakradhar94,
   author = {S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell},
   title = {Energy Minimization and Design for Testability},
   journal = {J. Electronic Testing: Theory and Applic.},
   volume = {5},
   pages = {55--64},
   month = feb,
   year = {1994}
}

@inproceedings{Chakraborty94,
   author = {T. J. Chakraborty and V. D. Agrawal},
   title = {Delay Independent Initialization of Sequential Circuits},
   booktitle = {Proc. 4th Great Lakes Symp. VLSI Design},
   pages = {228--230},
   month = mar,
   year = {1994}
}

@inproceedings{Heragu94,
   author = {K. Heragu and V. D. Agrawal and M. L. Bushnell},
   title = {{FACTS}: Fault Coverage Estimation by Test Vector Sampling},
   booktitle = {Proc. 12th IEEE VLSI Test Symp.},
   pages = {266--271},
   month = apr,
   year = {1994}
}

@article{Agrawal94a,
   author = {V. D. Agrawal},
   title = {A Tale of Two Designs: the Cheapest and the Most Economic},
   journal = {J. Electronic Testing: Theory and Applic.},
   volume = {5},
   number = {2/3},
   pages = {131--135},
   month = may,
   year = {1994}
}

@inproceedings{Heragu94a,
   author = {K. Heragu and M. L. Bushnell and V. D. Agrawal},
   title = {An Efficient Path Delay Fault Coverage Estimator},
   booktitle = {Proc. 31st Design Automation Conf.},
   pages = {516--521},
   month = jun,
   year = {1994}
}

@inproceedings{Chakradhar94a,
   author = {S. T. Chakradhar and A. Balakrishnan and V. D. Agrawal},
   title = {An Exact Algorithm for Selecting Partial Scan Flip-Flops},
   booktitle = {Proc. 31st Design Automation Conf.},
   pages = {81--86},
   month = jun,
   year = {1994}
}

@article{Agrawal94b,
   author = {V. D. Agrawal and C. J. Lin and P. Rutkowski and S. Wu and Y. Zorian},
   title = {Built-In Self-Test for Digital Integrated Circuits},
   journal = {AT\&T Tech. Jour.},
   volume = {73},
   number = {2},
   pages = {30--39},
   month = mar,
   year = {1994}
}

@inproceedings{Chakraborty94a,
   author = {T. J. Chakraborty and V. D. Agrawal},
   title = {Test Generation and Fault Simulation Algorithms for Sequential Circuits with Embedded {RAM}s},
   booktitle = {Proc. Third Asian Test Symp.},
   pages = {2--7},
   month = nov,
   year = {1994}
}

@inproceedings{Agrawal94c,
   author = {P. Agrawal and V. D. Agrawal and M. L. Bushnell and J. Sienicki},
   title = {Superlinear Speedup in Multiprocessing Environment},
   booktitle = {Proc. First International Workshop on Parallel Processing},
   pages = {261--265},
   month = dec,
   year = {1994}
}

@inproceedings{Sienicki95,
   author = {J. Sienicki and M. L. Bushnell and P. Agrawal and V. D. Agrawal},
   title = {An Asynchronous Algorithm for Sequential Circuit Test Generation on a Network of Workstations},
   booktitle = {Proc. 8th International Conf. VLSI Design},
   pages = {36--41},
   month = jan,
   year = {1995}
}

@inproceedings{Chakraborty95,
   author = {T. J. Chakraborty and V. D. Agrawal},
   title = {Robust Testing for Stuck-at Faults},
   booktitle = {Proc. 8th International Conf. VLSI Design},
   pages = {42--46},
   month = jan,
   year = {1995}
}

@inproceedings{Srinivas95,
   author = {M. K. Srinivas and J. Jacob and V. D. Agrawal},
   title = {Functional Test Generation for Non-Scan Sequential Circuits},
   booktitle = {Proc. 8th International Conf. VLSI Design},
   pages = {47--52},
   month = jan,
   year = {1995}
}

@inproceedings{Majhi95,
   author = {A. K. Majhi and J. Jacob and L. M. Patnaik and V. D. Agrawal},
   title = {An Efficient Automatic Test Generation System for Path Delay Faults in Combinational Circuits},
   booktitle = {Proc. 8th International Conf. VLSI Design},
   pages = {161--165},
   month = jan,
   year = {1995}
}

@inproceedings{Heragu95,
   author = {K. Heragu and V. D. Agrawal and M. L. Bushnell},
   title = {Statistical Methods for Delay Fault Coverage Analysis},
   booktitle = {Proc. 8th International Conf. VLSI Design},
   pages = {166--170},
   month = jan,
   year = {1995}
}

@article{Bhattacharya95,
   author = {D. Bhattacharya and P. Agrawal and V. D. Agrawal},
   title = {Test Generation for Path Delay Faults using Binary Decision Diagrams},
   journal = {IEEE Trans. Computers},
   volume = {44},
   pages = {434--447},
   month = mar,
   year = {1995}
}

@inproceedings{Chakradhar95,
   author = {S. T. Chakradhar and S.G. Rothweiler and V. D. Agrawal},
   title = {Redundancy Removal and Test Generation for Circuits with Non-{B}oolean Primitives},
   booktitle = {Proc. 13th IEEE VLSI Test Symp.},
   pages = {12--19},
   month = {April-May},
   year = {1995}
}

@inproceedings{Chakraborty95a,
   author = {T. J. Chakraborty and V. D. Agrawal},
   title = {Simulation of At-Speed Tests for Stuck-at Faults},
   booktitle = {Proc. 13th IEEE VLSI Test Symp.},
   pages = {216--220},
   month = {April-May},
   year = {1995}
}

@article{Heragu95a,
   author = {K. Heragu and V. D. Agrawal and M. L. Bushnell},
   title = {Fault Coverage Estimation by Test Vector Sampling},
   journal = {IEEE Trans. CAD},
   volume = {14},
   pages = {590--596},
   month = may,
   year = {1995},
   note = {Correction, August 1995, p. 1037}
}

@article{Chakradhar95a,
   author = {S. T. Chakradhar and M.A. Iyer and V. D. Agrawal},
   title = {Energy Models for Delay Testing},
   journal = {IEEE Trans. CAD},
   volume = {14},
   pages = {728--739},
   month = jun,
   year = {1995}
}

@article{Chakradhar95b,
   author = {S. T. Chakradhar and A. Balakrishnan and V. D. Agrawal},
   title = {An Exact Algorithm for Selecting Partial Scan Flip-Flops},
   journal = {J. Electronic Testing: Theory and Applic.},
   volume = {7},
   number = {1/2},
   pages = {83--93},
   month = aug,
   year = {1995}
}

@article{Kanjilal95,
   author = {S. Kanjilal and S. T. Chakradhar and V. D. Agrawal},
   title = {Test Function Embedding Algorithms with Application to Interconnected Finite State Machines},
   journal = {IEEE Trans. CAD},
   volume = {14},
   pages = {1115--1127},
   month = sep,
   year = {1995}
}

@article{Agrawal95,
   author = {V. D. Agrawal and S. T. Chakradhar},
   title = {Combinational {ATPG} Theorems for Identifying Untestable Faults in Sequential Circuits},
   journal = {IEEE Trans. CAD},
   volume = {14},
   pages = {1155--1160},
   month = sep,
   year = {1995}
}

@inproceedings{Sienicki95a,
   author = {J. Sienicki and M. L. Bushnell and P. Agrawal and V. D. Agrawal},
   title = {An Adaptive Distributed Algorithm for Sequential Circuit Test Generation},
   booktitle = {Proc. EURO-DAC},
   pages = {236--241},
   month = sep,
   year = {1995}
}

@article{Kanjilal95a,
   author = {S. Kanjilal and S. T. Chakradhar and V. D. Agrawal},
   title = {A Partition and Resynthesis Approach to Testable Design of Large Circuits},
   journal = {IEEE Trans. CAD},
   volume = {14},
   pages = {1268--1276},
   month = oct,
   year = {1995}
}

@inproceedings{Gharaybeh95,
   author = {M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title = {Classification and Test Generation for Path-Delay Faults using Single Stuck-Fault Tests},
   booktitle = {Proc. International Test Conf.},
   pages = {139--148},
   month = oct,
   year = {1995}
}

@inproceedings{Agrawal95a,
   author = {V. D. Agrawal and T. J. Chakraborty},
   title = {High-Performance Circuit Testing with Slow-Speed Testers},
   booktitle = {Proc. International Test Conf.},
   pages = {302--310},
   month = oct,
   year = {1995}
}

@inproceedings{Srinivas95a,
   author = {M. K. Srinivas and V. D. Agrawal and M. L. Bushnell},
   title = {Functional Test Generation for Path Delay Faults},
   booktitle = {Proc. Fourth Asian Test Symp.},
   pages = {339--345},
   month = nov,
   year = {1995}
}

@inproceedings{Bose95,
   author = {S. Bose and V. D. Agrawal},
   title = {Sequential Logic Path Delay Test Generation by Symbolic Analysis},
   booktitle = {Proc. Fourth Asian Test Symp.},
   pages = {353--359},
   month = nov,
   year = {1995}
}

@inproceedings{Agrawal96,
   author = {V. D. Agrawal},
   title = {Science, Technology and the Indian Society, {A} Keynote Talk},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {6--8},
   month = jan,
   year = {1996}
}

@inproceedings{Chakraborty96,
   author = {T. J. Chakraborty and V. D. Agrawal},
   title = {Design for High Speed Testability of Stuck-at Faults},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {53--56},
   month = jan,
   year = {1996}
}

@inproceedings{Pappu96,
   author = {L. Pappu and M. L. Bushnell and V. D. Agrawal},
   title = {Statistical Path-Delay Fault Coverage Estimation for Synchronous Sequential Circuits},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {290--295},
   month = jan,
   year = {1996}
}

@inproceedings{Agrawal96a,
   author = {V. D. Agrawal and D. Lee},
   title = {Characteristic Polynomial Method for Verification and Test of Combinational Circuits},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {341--342},
   month = jan,
   year = {1996}
}

@inproceedings{Majhi96,
   author = {A. K. Majhi and J. Jacob and L. M. Patnaik and V. D. Agrawal},
   title = {On Test Coverage of Path-Delay Faults},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {418--421},
   month = jan,
   year = {1996}
}

@inproceedings{Heragu96,
   author = {K. Heragu and J. H. Patel and V. D. Agrawal},
   title = {Improving Accuracy in Path-Delay Fault Coverage Estimation},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {422--425},
   month = jan,
   year = {1996}
}

@inproceedings{Gharaybeh96,
   author = {M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title = {Parallel Pattern Concurrent Fault Simulation of Path-Delay Faults with Single-Input Change Tests},
   booktitle = {Proc. 9th International Conf. VLSI Design},
   pages = {426--431},
   month = jan,
   year = {1996}
}

@inproceedings{Einspahr96,
   author = {K. L. Einspahr and S. C. Seth and V. D. Agrawal},
   title = {Improving Circuit Testability by Clock Control},
   booktitle = {Proc. Sixth Great Lakes Symp. on VLSI},
   pages = {288--293},
   month = mar,
   year = {1996}
}

@inproceedings{Heragu96a,
   author = {K. Heragu and J. H. Patel and V. D. Agrawal},
   title = {Segment Delay Faults: {A} New Fault Model},
   booktitle = {Proc. 14th IEEE VLSI Test Symp.},
   pages = {32--39},
   month = {April-May},
   year = {1996}
}

@article{Srinivas96,
   author = {M. K. Srinivas and J. Jacob and V. D. Agrawal},
   title = {Functional Test Generation for Synchronous Sequential Circuits},
   journal = {IEEE Trans. on CAD},
   volume = {15},
   pages = {831--843},
   month = jul,
   year = {1996}
}

@inproceedings{Agrawal96b,
   author = {V. D. Agrawal},
   title = {Testing in a Mixed-Signal World},
   booktitle = {Proc. 9th Annual IEEE International ASIC Conf.},
   pages = {241--244},
   month = oct,
   year = {1996}
}

@inproceedings{Gharaybeh96a,
   author = {M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title = {An Exact Non-Enumerative Fault Simulator for Path-Delay Faults},
   booktitle = {Proc. International Test Conf.},
   pages = {276--285},
   month = oct,
   year = {1996}
}

@inproceedings{Agrawal96c,
   author = {V. D. Agrawal and R. D. Blanton and M. Damiani},
   title = {Synthesis of Self-Testing Finite State Machines from High-Level Specification},
   booktitle = {Proc. International Test Conf.},
   pages = {757--766},
   month = oct,
   year = {1996}
}

@inproceedings{Agrawal96e,
   author = {V. D. Agrawal and M. L. Bushnell and Q. Lin},
   title  = {{Redundancy Identification using Transitive Closure}},
   booktitle = {Proc. Fifth IEEE Asian Test Symp.},
   pages  = {4--9},
   month  = nov,
   year   = {1996}
}

@misc{}

@conference{Heragu96b,
title = {{SIGMA: A Simulator for Segment Delay Faults}},
author = {K. Heragu and J. H. Patel and V. D. Agrawal},
booktitle = {Proc. IEEE ACM International Conf. on CAD},
pages = {502--508},
month = nov,
year = {1996}
}

@inproceedings{Srinivas97,
   author = {M. K. Srinivas and M. L. Bushnell and V. D. Agrawal},
   title = {{Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation}},
   booktitle = {Proc. 10th International Conf. on VLSI Design},
   pages = {88--94},
   month = jan,
   year = {1997}
}

@inproceedings{Agrawal97,
   author = {V. D. Agrawal},
   title = {Low-Power Design by Hazard Filtering},
   booktitle = {Proc. 10th International Conf. on VLSI Design},
   pages = {193--197},
   month = jan,
   year = {1997}
}

@inproceedings{Jacob97,
   author = {J. Jacob and P. S. Sivakumar and V. D. Agrawal},
   title = {Adder and Comparator Synthesis with Exclusive-{OR} Transform of Inputs},
   booktitle = {Proc. 10th International Conf. on VLSI Design},
   pages = {514--515},
   month = jan,
   year = {1997}
}

@incollection{Chakradhar97a,
   author = {S. T. Chakradhar and V. D. Agrawal},
   title = {VLSI Design},
   booktitle = {Encyclopedia of Microcomputers},
   publisher = {Marcel Dekker, Inc.},
   address = {New York},
   year = {1997},
   editor =  {A. Kent and J. G. Williams},
   pages = {97--111},
   note = {Volume 20}
}

@article{Chou97,
   author = {R. M. Chou and K. K. Saluja and V. D. Agrawal},
   title = {Scheduling Tests for VLSI Systems Under Power Constraints},
   journal = {IEEE Trans. VLSI Systems},
   volume = {5},
   number = {2},
   pages = {175--185},
   month = jun,
   year = {1997}
}

@article{Heragu97a,
   author = {K. Heragu and V. D. Agrawal and M. L. Bushnell and J. H. Patel},
   title = {Improving a Nonenumerative Method to Estimate Path Delay Fault Coverage},
   journal = {IEEE Trans. CAD},
   volume  = {16},
   number  = {7},
   pages   = {759--762},
   month   = jul,
   year    = {1997}
}

@article{Gharaybeh97,
   author  = {M. A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title   = {Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests},
   journal = {J. Electronic Testing: Theory and Applications},
   volume  = {11},
   number  = {1},
   pages   = {55--67},
   month   = aug,
   year    = {1997}
}

@article{Chakraborty97a,
   author  = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title   = {On Variable Clock Methods for Path Delay Testing of Sequential Circuits},
   journal = {IEEE Trans. CAD},
   volume  = {16},
   number  = {11},
   pages   = {1237--1249},
   month   = nov,
   year    = {1997}
}

@article{Chakradhar97b,
   author  = {S. T. Chakradhar and S. G. Rothweiler and V. D. Agrawal},
   title   = {Redundancy Removal and Test Generation for Circuits with Non-{B}oolean Primitives},
   journal = {IEEE Trans. CAD},
   volume  = {16},
   number  = {11},
   pages   = {1370--1377},
   month   = nov,
   year    = {1997}
}

@inproceedings{Bose97,
   author  = {S. Bose and V. D. Agrawal and T. G. Szymanski},
   title   = {Algorithms for Switch Level Delay Fault Simulation},
   booktitle = {Proc. International Test Conf.},
   pages   = {982-991},
   year    = {1997}
}

@inproceedings{Chakraborty97b,
   author  = {T. J. Chakraborty and V. D. Agrawal},
   title   = {Effective Path Selection for Delay Fault Testing of Sequential Circuits},
   booktitle = {Proc. International Test Conf.},
   pages   = {998--1003},
   year    = {1997}
}

@inproceedings{Heragu97b,
   author  = {K. Heragu and J. H. Patel and V. D. Agrawal},
   title   = {Fast Identification of Untestable Delay Faults Using Implications},
   booktitle = {Proc. International Conf. CAD},
   pages   = {642--647},
   year    = {1997}
}

@inproceedings{Chavda98,
   author  = {P. Chavda and J. Jacob and V. D. Agrawal},
   title   = {Optimizing Logic Using {B}oolean Transforms},
   booktitle = {Proc. 11th International Conf. VLSI Design},
   pages   = {218--221},
   year    = {1998}
}

@inproceedings{Majhi98a,
   author  = {A. K. Majhi and V. D. Agrawal},
   title   = {Mixed-Signal Test},
   booktitle = {Proc. 11th International Conf. VLSI Design},
   pages   = {285--288},
   year    = {1998}
}

@inproceedings{Majhi98b,
   author  = {A. K. Majhi and V. D. Agrawal},
   title   = {Tutorial: Delay Fault Models and Coverage},
   booktitle = {Proc. 11th International Conf. VLSI Design},
   pages   = {364--369},
   year    = {1998}
}

@inproceedings{Majumder98,
   author  = {S. Majumder and V. D. Agrawal and M. L. Bushnell},
   title   = {Path Delay Testing: Variable-Clock Versus Rated-Clock},
   booktitle = {Proc. 11th International Conf. VLSI Design},
   pages   = {470--475},
   year    = {1998}
}

@inproceedings{Agrawal98a,
   author  = {V. D. Agrawal and S. C. Seth},
   title   = {Mutually Disjoint Signals and Probability Calculation in Digital Circuits},
   booktitle = {Proc. 8th Great Lakes Symp. VLSI},
   pages   = {307--312},
   year    = {1998}
}

@article{Gharaybeh98a,
   author  = {M. A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title   = {The Path-Status Graph with Application to Delay Fault Simulation},
   journal = {IEEE Trans. CAD},
   volume  = {17},
   number  = {4},
   pages   = {324--332},
   month   = apr,
   year    = {1998}
}

@inproceedings{Agrawal98b,
   author  = {V. D. Agrawal},
   title   = {Test Education for VLSI Systems Design Engineers},
   booktitle = {Proc. Computer Soc. Workshop on VLSI},
   pages   = {62--64},
   year    = {1998}
}

@inproceedings{Majumder98b,
   author  = {S. Majumder and V. D. Agrawal and M. L. Bushnell},
   title   = {On Delay-Untestable Paths and Stuck-Fault Redundancy},
   booktitle = {Proc. 16th IEEE VLSI Test Symp.},
   pages   = {194--199},
   year    = {1998}
}

@article{Bose98a,
   author  = {S. Bose and P. Agrawal and V. D. Agrawal},
   title   = {A Rated-Clock Test Method for Path Delay Faults},
   journal = {IEEE Trans. VLSI Systems},
   volume  = {6},
   number  = {2},
   pages   = {323--331},
   month   = jun,
   year    = {1998}
}

@article{Pappu98,
   author  = {L. Pappu and M. L. Bushnell and V. D. Agrawal and S. Mandyam-Komar},
   title   = {Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits},
   journal = {J. Electronic Testing: Theory and Applications},
   volume  = {12},
   number  = {3},
   pages   = {239--254},
   month   = jun,
   year    = {1998}
}

@article{Agrawal98c,
   author  = {V. D. Agrawal and D. Lee and H. Wo\'{z}niakowski},
   title   = {Numerical Computation of Characteristic Polynomials of {B}oolean Functions and its Applications},
   journal = {Numerical Algorithms},
   volume  = {17},
   pages   = {261--278},
   year    = {1998}
}

@article{Bose98b,
   author  = {S. Bose and P. Agrawal and V. D. Agrawal},
   title   = {Deriving Logic Systems for Path Delay Test Generation},
   journal = {IEEE Trans. Computers},
   volume  = {47},
   number  = {8},
   pages   = {829--846},
   month   = aug,
   year    = {1998}
}

@article{Gharaybeh98b,
   author = {M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal},
   title  = {A Parallel-Vector Concurrent-Fault Simulator and Generation of Single-Input-Change Tests for Path-Delay Faults},
   journal = {IEEE Trans. CAD},
   volume = {17},
   number = {9},
   pages  = {873--876},
   month  = sep,
   year   = {1998}
}

@inproceedings{Parodi98,
   author = {C. G. Parodi and V. D. Agrawal and M. L. Bushnell and S. Wu},
   title  = {A Non-Enumerative Path Delay Fault Simulator for Sequential Circuits},
   booktitle = {Proc. International Test Conf.},
   pages  = {934--943},
   year   = {1998}
}

@inproceedings{Gharaybeh98c,
   author = {M.A. Gharaybeh and V. D. Agrawal and M. L. Bushnell},
   title  = {False Path Removal Using Delay Fault Simulation},
   booktitle = {Proc. 7th IEEE Asian Test Symp.},
   pages  = {82--87},
   year   = {1998}
}

@article{Agrawal98d,
   author  = {V. D. Agrawal},
   title   = {Design of Mixed-Signal Systems for Testability},
   journal = {INTEGRATION, The VLSI Journal},
   volume  = {26},
   pages   = {141--150},
   year    = {1998}
}

@inproceedings{Agrawal99,
   author  = {V. D. Agrawal and M. L. Bushnell and G. Parthasarathy and R. Ramadoss},
   title   = {Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method},
   booktitle = {Proc. 12th International Conf. VLSI Design},
   pages   = {434--439},
   year    = {1999}
}

@inproceedings{Heragu99,
   author  = {K. Heragu and J. H. Patel and V. D. Agrawal},
   title   = {A Test Generator for Segment Delay Faults},
   booktitle = {Proc. 12th International Conf. VLSI Design},
   pages   = {484--491},
   year    = {1999}
}

@inproceedings{Majumder99,
   author  = {S. Majumder and B. B. Bhattacharya and V. D. Agrawal and M. L. Bushnell},
   title   = {A Complete Characterization of Path Delay Faults through Stuck-at Faults},
   booktitle = {Proc. 12th International Conf. VLSI Design},
   pages   = {492--497},
   year    = {1999}
}

@inproceedings{Kim99,
   author  = {Y. C. Kim and V. D. Agrawal and K. K. Saluja},
   title   = {A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability},
   booktitle = {Proc. 9th Great Lakes Symp. on VLSI},
   pages   = {300--303},
   year    = {1999}
}

@inproceedings{Thaker99,
   author  = {P. A. Thaker and V. D. Agrawal and M. E. Zaghloul},
   title   = {Validation Vector Grade ({VVG}): A New Coverage Metric for Validation and Test},
   booktitle = {Proc. 17th IEEE VLSI Test Symp.},
   pages   = {182--188},
   year    = {1999}
}

@inproceedings{Peng99,
   author  = {Q. Peng and V. D. Agrawal and J. Savir},
   title   = {On the Guaranteed Failing and Working Frequencies in Path Delay Fault Analysis},
   booktitle = {Proc. 16th IEEE Instrumentation and Measurement Technology Conf.},
   pages   = {1794--1799},
   year    = {1999}
}

@inproceedings{Agrawal00,
   author  = {V. D. Agrawal},
   title   = {Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation},
   booktitle = {Proc. 13th International Conf. VLSI Design},
   pages   = {304--309},
   month   = jan,
   year    = {2000}
}

@inproceedings{Tsai00,
   author  = {H.-C. Tsai and K.-T. Cheng and V. D. Agrawal},
   title   = {A Testability Metric for Path Delay Faults and Its Application},
   booktitle = {Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC)},
   pages   = {593--598},
   month   = jan,
   year    = {2000}
}

@inproceedings{deSousa00,
   author  = {J. T. deSousa and V. D. Agrawal},
   title   = {Reducing the Complexity of Defect Level Modeling using the Clustering Effect},
   booktitle = {Proc. Design, Automation and Test in Europe (DATE) Conf.},
   month   = mar,
   year    = {2000},
   pages   = {640--644}
}

@article{Chakraborty00a,
   author  = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title   = {Path Delay Fault Simulation of Sequential Circuits},
   journal = {IEEE Trans. VLSI Systems},
   volume  = {8},
   month   = apr,
   year    = {2000},
   pages   = {223--228}
}

@article{Majhi00,
   author  = {A. K. Majhi and V. D. Agrawal and J. Jacob and L. M. Patnaik},
   title   = {Line Coverage of Path Delay Faults},
   journal = {IEEE Trans. VLSI Systems},
   volume  = {8},
   pages   = {610--614},
   month   = oct,
   year    = {2000}
}

@article{Gharaybeh00,
   author =  {M. A. Gharaybeh and V. D. Agrawal and M. L. Bushnell and C. G. Parodi},
   title =   {False-Path Removal using Delay Fault Simulation},
   journal = {J. Electronic Testing: Theory and Applic.},
   volume =  {16},
   month =   oct,
   year =    {2000},
   pages =   {463--476}
}

@inproceedings{Thaker00,
   author =  {P. A. Thaker and V. D. Agrawal and M. E. Zaghloul},
   title =   {Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits},
   booktitle = {Proc. International Test Conf.},
   month =   oct,
   year =    {2000},
   pages =   {940--949}
}

@inproceedings{Giani00,
   author =  {A. Giani and S. Sheng and M. Hsiao and V. D. Agrawal},
   title =   {Compaction-Based Test Generation Using State and Fault Information},
   booktitle = {Proc. 9th Asian Test Symp.},
   month =   dec,
   pages =   {159--164},
   year =    {2000}
}

@book{Bushnell00,
   author = {M. L. Bushnell and V. D. Agrawal},
   title =  {Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits},
   publisher = {Kluwer Academic Publishers},
   address = {Boston},
   year =   {2000}
}

@article{Chakraborty00b,
   author  = {T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell},
   title   = {Improving Path Delay Testability of Sequential Circuits},
   journal = {IEEE Trans. VLSI Systems},
   volume  = {8},
   month   = dec,
   pages   = {736--741},
   year    = {2000}
}

@inproceedings{Kim01a,
   author  =  {Y. C. Kim and V. D. Agrawal and K. K. Saluja},
   title   =  {Combinational Test Generation for Acyclic Sequential Circuits using a Balanced {ATPG} Model},
   booktitle = {Proc. 14th International Conf. VLSI Design},
   month   =  jan,
   pages   =  {143--148},
   year    =  {2001}
}

@inproceedings{Giani01a,
   author =  {A. Giani and S. Sheng and M. Hsiao and V. D. Agrawal},
   title =   {Efficient Spectral Techniques for Sequential {ATPG}},
   booktitle = {Proc. Design, Automation and Test in Europe (DATE) Conf.},
   month =   mar,
   pages = {204--208},
   year =    {2001}
}

@inproceedings{Giani01b,
   author =  {A. Giani and S. Sheng and M. Hsiao and V. D. Agrawal},
   title =   {Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment},
   booktitle = {Proc. 19th IEEE VLSI Test Symp.},
   month =    apr,
   pages =    {163--168},
   year =     {2001}
}

@inproceedings{Kim01b,
   author =  {Y. C. Kim and V. D. Agrawal and K. K. Saluja},
   title =   {Combinational Test Generation for Various Classes of Acyclic Sequential Circuits},
   booktitle = {Proc. International Test Conf.},
   pages   = {1078--1087},
   month =   oct,
   year =    {2001}
}

@inproceedings{Kim02a,
   author =  {Y. C. Kim and V. D. Agrawal and K. K. Saluja},
   title =   {Multiple Faults: Modeling, Simulation and Test},
   booktitle = {Proc. 7th ASPDAC/15th International Conf. VLSI Design},
   pages = {592--597},
   month = jan,
   year = {2002}
}

@inproceedings{Gaur02,
   author =  {V. Gaur and V. D. Agrawal and M. L. Bushnell},
   title  =  {A New Transitive Closure Algorithm with Application to Redundancy Identification},
   booktitle = {Proc. 1st International Workshop on Electronic, Design and Test Applications (DELTA'02)},
   month  = jan,
   pages  = {496--500},
   year   = {2002}
}

@article{Giani01c,
   author =  {A. Giani and S. Sheng and M. Hsiao and V. D. Agrawal},
   title =   {Compaction-Based Test Generation Using State and Fault Information},
   journal = {J. Electronic Testing: Theory and Applic.},
   year    = {2002},
   volume  = {18},
   number  = {1},
   pages   = {63--72},
   month   = feb
}

@inproceedings{Sathe02,
   author  = {A. D. Sathe and M. L. Bushnell and V. D. Agrawal},
   title   = {Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects},
   booktitle= {Proc. International Test Conf.},
   pages   = {375--383},
   month   = oct,
   year    = {2002}
}

@inproceedings{Prasad02,
   author  = {A. V. S. S. Prasad and V. D. Agrawal and M. V. Atre},
   title   = {A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Cells},
   booktitle= {Proc. International Test Conf.},
   month   = oct,
   pages   = {391--397},
   year    = {2002}
}

@inproceedings{Agrawal03,
   author  = {V. D. Agrawal and D. H. Baik and Y. C. Kim and K. K. Saluja},
   title   = {Exclusive Test and Its Applications in Fault Diagnosis},
   pages   = {143--148},
   booktitle= {Proc. 16th International Conf. VLSI Design},
   month   = jan,
   year    = {2003}
}

@inproceedings{Mehta03,
   author  = {V. Mehta and K. Dave and V. D. Agrawal and M. L. Bushnell},
   title   = {A Fault-Independent Transitive Closure Algorithm for Redundancy Identification},
   pages   = {149--154},
   booktitle= {Proc. 16th International Conf. VLSI Design},
   month   = jan,
   year    = {2003}
}

@inproceedings{Rao03,
   author  = {L. Rao and M. L. Bushnell and V. D. Agrawal},
   title   = {Graphical {$I_{DDQ}$} Signatures Reduce Defect Level and Yield Loss},
   pages   = {353--360},
   booktitle= {Proc. 16th International Conf. VLSI Design},
   month   = jan,
   year    = {2003}
}

@inproceedings{Raja03,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {Minimum Dynamic Power {CMOS} Circuit Design by a Reduced Constraint Set Linear Program},
   pages   = {527--532},
   booktitle= {Proc. 16th International Conf. VLSI Design},
   month   = jan,
   year    = {2003}
}

@article{Thaker03,
   author =  {P. A. Thaker and V. D. Agrawal and M. E. Zaghloul},
   title =   {A Test Evaluation Technique for {VLSI} Circuits Using Register-Transfer Level Fault Modeling},
   journal = {IEEE Trans. CAD},
   volume  = {22},
   number  = {8},
   pages   = {1104--1113},
   month   = aug,
   year    = {2003}
}

@inproceedings{Agrawal_2_03,
   author  = {V. D. Agrawal and A. V. S. S. Prasad and M. V. Atre},
   title   = {Fault Collapsing via Functional Dominance},
   booktitle= {Proc. International Test Conf.},
   month   = sep,
   pages   = {274--280},
   year    = {2003}
}

@inproceedings{Raja_1_04,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {{CMOS} Circuit Design for Minimum Dynamic Power and Highest Speed},
   booktitle= {Proc. 17th International Conf. VLSI Design},
   pages    = {1035--1040},
   month   = jan,
   year    = {2004}
}

@inproceedings{Raja_2_04,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {A Tutorial on the Emerging Nanotechnology Devices},
   booktitle= {Proc. 17th International Conf. VLSI Design},
   pages   = {343--360},
   month   = jan,
   year    = {2004}
}

@article{Majumder_04,
   author  = {S. Majumder and B. B. Bhattacharya and V. D. Agrawal and M. L. Bushnell},
   title   = {New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults},
   journal = {Journal of Computer Science and Technology (Academia Sinica)},
   volume  = {19},
   number  = {6},
   month   = nov,
   pages   = {955--964},
   year    = {2004}
}

@inproceedings{Zhang04,
   author  = {J. Zhang and M. L. Bushnell and V. D. Agrawal},
   title   = {On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits},
   booktitle= {Proc. International Test Conf.},
   month   = oct,
   year    = {2004},
   pages   = {617--626}
}

@inproceedings{Raja05a,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {Variable Input Delay CMOS Logic for Low Power Design},
   booktitle= {Proc. 18th International Conf. VLSI Design},
   month   = jan,
   year    = {2005},
   pages   = {598--605}
}

@inproceedings{Dave05,
   author  = {K. Dave and V. D. Agrawal and M. L. Bushnell},
   title   = {Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies},
   booktitle= {Proc. 18th International Conf. VLSI Design},
   month   = jan,
   year    = {2005},
   pages   = {723--729}
}

@inproceedings{Sandireddy05,
   author  = {R. K. K. R. Sandireddy and V. D. Agrawal},
   title   = {Diagnostic and Detection Fault Collapsing for Multiple Output Circuits},
   booktitle= {Proc. Design, Automation and Test in Europe (DATE'05)},
   month   = mar,
   pages   = {1014--1019},
   year    = {2005}
}

@inproceedings{Hu05a,
   author  = {F. Hu and V. D. Agrawal},
   title   = {Dual-Transition Glitch Filtering in Probabilistic Waveform Power Estimation},
   booktitle= {Proc. 15th IEEE Great Lakes Symp. on VLSI},
   month   = apr,
   pages   = {357--360},
   year    = {2005}
}

@article{Kim05,
   author  = {Y. C. Kim and V. D. Agrawal and K. K. Saluja},
   title   = {Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits},
   journal = {IEEE Trans. CAD},
   volume  = {24},
   number  = {6},
   month   = jun,
   pages   = {948--956},
   year    = {2005}
}

@inproceedings{Uppalapati05,
   author  = {S. Uppalapati and M. L. Bushnell and V. D. Agrawal},
   title   = {Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells},
   booktitle= {Proc. 9th VLSI Design \& Test Symp. (VDAT'05)},
   month   = aug,
   pages   = {41--49},
   year    = {2005}
}

@inproceedings{Mudlapur05a,
   author  = {A. S. Mudlapur and V. D. Agrawal and A. D. Singh},
   title   = {A Novel Random Access Scan Flip-Flop Design},
   booktitle= {Proc. 9th VLSI Design \& Test Symp. (VDAT'05)},
   month   = aug,
   pages   = {226--236},
   year    = {2005}
}

@inproceedings{Doshi05a,
   author  = {A. S. Doshi and V. D. Agrawal},
   title   = {Independence Fault Collapsing},
   booktitle= {Proc. 9th VLSI Design \& Test Symp. (VDAT'05)},
   month   = aug,
   pages   = {357--366},
   year    = {2005}
}

@inproceedings{Raja05b,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits},
   booktitle= {Proc. Power and Timing Modeling, Optimization and Simulation Workshop (PATMOS'05)},
   month   = sep,
   pages   = {436--445},
   year    = {2005}
}

@inproceedings{Lu05a,
   author  = {Y. Lu and V. D. Agrawal},
   title   = {Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for ${V}_{th}$ Assignment and Path Balancing},
   booktitle= {Proc. Power and Timing Modeling, Optimization and Simulation Workshop (PATMOS'05)},
   month   = sep,
   pages   = {217--226},
   year    = {2005}
}

@inproceedings{Hu05b,
   author  = {F. Hu and V. D. Agrawal},
   title   = {Enhanced Dual-Transition Probabilistic Power Estimation With Selective Supergate Analysis},
   booktitle= {Proc. IEEE International Conf. on Computer Design},
   month   = oct,
   pages   = {366--369},
   year    = {2005}
}

@inproceedings{Mudlapur05b,
   author  = {A. S. Mudlapur and V. D. Agrawal and A. D. Singh},
   title   = {A Random Access Scan Architecture to Reduce Hardware Overhead},
   booktitle= {Proc. International Test Conf.},
   month   = nov,
   year    = {2005},
   note    = {Paper 15.1}
}

@inproceedings{Agrawal05a,
   author  = {V. D. Agrawal and A. S. Doshi},
   title   = {Concurrent Test Generation},
   booktitle={Proc. 14th IEEE Asian Test Symp.},
   month   = dec,
   year    = {2005},
   pages   = {294--297}
}

@inproceedings{Kantipudi06a,
   author  = {K. R. Kantipudi and V. D. Agrawal},
   title   = {On the Size and Generation of Minimal {N}-Detection Tests},
   booktitle={Proc. 19th International Conf. VLSI Design},
   month   = jan,
   year    = {2006},
   pages   = {425--430}
}

@article{Raja06a,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {Transistor Sizing of Logic Gates to Maximize Input Delay Variability},
   journal = {Journal of Low Power Electronics},
   volume  = {2},
   number  = {1},
   month   = apr,
   year    = {2006},
   pages   = {121--128}
}

@inproceedings{Bose06a,
   author  = {V. D. Agrawal and S. Bose and V. Gangaram},
   title   = {Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring},
   booktitle={Proc. 24th IEEE VLSI Test Symp.},
   month   = may,
   year    = {2006},
   pages   = {88--93}
}

@inproceedings{Yogi06a,
   author  = {N. Yogi and V. D. Agrawal},
   title   = {Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests},
   booktitle= {Proc. 10th VLSI Design \& Test Symp. (VDAT'06)},
   month   = aug,
   pages   = {407--417},
   year    = {2006}
}

@inproceedings{Hu06a,
   author  = {F. Hu and V. D. Agrawal},
   title   = {Input-Specific Dynamic Power Optimization for VLSI Circuits},
   booktitle= {Proc. Int. Symp. on Low Power Electronics and Design (ISLPED'06)},
   month   = oct,
   pages   = {232--237},
   year    = {2006}
}

@inproceedings{Bose06b,
   author  = {S. Bose and V. D. Agrawal},
   title   = {Fault Coverage Estimation for Non-Random Functional Input Sequences},
   booktitle={Proc. Int. Test Conf.},
   month   = oct,
   year    = {2006},
   pages   = {19.3.1--19.3.10}
}

@inproceedings{Yogi06b,
   author  = {N. Yogi and V. D. Agrawal},
   title   = {Spectral {RTL} Test Generation for Gate-Level Stuck-at Faults},
   booktitle= {Proc. 15th IEEE Asian Test Symp. (ATS06)},
   month   = nov,
   year    = {2006},
   pages   = {83--88}
}

@article{Lu06a,
   author  = {Y. Lu and V. D. Agrawal},
   title   = {{CMOS} Leakage and Glitch Minimization for Power-Performance Tradeoff},
   journal = {Journal of Low Power Electronics},
   volume  = {2},
   number  = {3},
   month   = dec,
   year    = {2006},
   pages   = {378--387}
}

@inproceedings{Lu07a,
   author  = {Y. Lu and V. D. Agrawal},
   title   = {Statictical Leakage and Timing Optimization for Submicron Process Variation},
   booktitle={Proc. 20th International Conf. VLSI Design},
   month   = jan,
   year    = {2007},
   pages   = {439--444}
}

@inproceedings{Yogi7a,
   author  = {N. Yogi and V. D. Agrawal},
   title   = {Spectral {RTL} Test Generation for Microprocessors},
   booktitle={Proc. 20th International Conf. VLSI Design},
   month   = jan,
   year    = {2007},
   pages   = {473--478}
}

@inproceedings{Kantipudi07a,
   author  = {K. R. Kantipudi and V. D. Agrawal},
   title   = {A Reduced Complexity Algorithm for Minimizing {$N$}-Detect Tests},
   booktitle={Proc. 20th International Conf. VLSI Design},
   month   = jan,
   year    = {2007},
   pages   = {492--497}
}

@inproceedings{Yogi7b,
   author  = {N. Yogi and V. D. Agrawal},
   title   = {Transition Delay Fault Testing of Microprocessors by Spectral Method},
   booktitle={Proc. 39th Southeastern Symp. on System Theory},
   month   = mar,
   year    = {2007},
   pages   = {283--287}
}

@inproceedings{Bose07a,
   author  = {S. Bose and V. D. Agrawal},
   title   = {Delay Test Quality Evaluation Using Bounded Gate Delays},
   booktitle={Proc. 25th IEEE VLSI Test Symp.},
   month   = may,
   pages   = {23--28},
   year    = {2007}
}

@inproceedings{Sandireddy07,
   author  = {R. K. K. R. Sandireddy and V. D. Agrawal},
   title   = {Using Hierarchy in Design Automation: The Fault Collapsing Problem},
   booktitle= {Proc. 11th VLSI Design \& Test Symp. (VDAT'07)},
   month   = aug,
   pages   = {174--184},
   year    = {2007}
}

@inproceedings{Bose07b,
   author  = {S. Bose and V. D. Agrawal},
   title   = {Estimating Stuck Fault Coverage in Sequential Circuits Using State Traversal and Entropy Analysis},
   booktitle={Proc. Int. Test Conf.},
   month   = oct,
   year    = {2007},
   pages   = {26.1.1--26.1.10}
}

@inproceedings{Bose07c,
   author  = {S. Bose and H. Grimes and V. D. Agrawal},
   title   = {Delay Fault Simulation with Bounded Gate Delay Model},
   booktitle={Proc. Int. Test Conf.},
   month   = oct,
   year    = {2007},
   pages   = {26.3.1--26.3.10}
}

@inproceedings{Khan07a,
   author  = {O. I. Khan and M. L. Bushnell and S. K. Devanathan and V. D. Agrawal},
   title   = {{SPARTAN:} A Spectral and Information Theoretic Approach to Partial Scan},
   booktitle={Proc. Int. Test Conf.},
   month   = oct,
   year    = {2007},
   note   = {Paper 21.1}
}

@article{Rao07,
   author  = {L. Rao and M. L. Bushnell and V. D. Agrawal},
   title   = {Graphical ${I}_{DDQ}$ Signatures Reduce Defect Level and Yield Loss},
   journal = {IEEE Trans. VLSI Systems},
   volume  = {15},
   number  = {11},
   pages   = {1245--1255},
   month   = nov,
   year    = {2007}
}

@inproceedings{Wang08a,
   author  = {F. Wang and V. D. Agrawal},
   title   = {Single Event Upset: An Embedded Tutorial},
   booktitle={Proc. 21st International Conf. VLSI Design},
   month   = jan,
   year    = {2008},
   pages   = {429--434}
}

@inproceedings{Lu08a,
   author  = {Y. Lu and V. D. Agrawal},
   title   = {Total Power Minimization in Glitch-Free {CMOS} Circuits Considering Process Variation},
   booktitle={Proc.~21st International Conf. VLSI Design},
   month   = jan,
   year    = {2008},
   pages   = {531--536}
}

@inproceedings{Yogi_03_08a,
Author     = {N. Yogi and V. D. Agrawal},
title      = {{$N$}-Model Tests for {VLSI} Circuits},
booktitle  = {Proc.~40th Southeastern Symp. System Theory},
month      = mar,
year       = {2008},
pages      = {242--246}
}

@inproceedings{Wang_03_08b,
author     = {F. Wang and V. D. Agrawal},
title      = {{Soft Error Rate Determination for Nanometer CMOS VLSI Logic}},
booktitle  = {Proc.~40th Southeastern Symp.~System Theory},
month      = mar,
year       = {2008},
pages      = {324--328}
}

@inproceedings{Sethuram_4_08,
author     = {R. Sethuram and M. L. Bushnell and V. D. Agrawal},
title      = {{Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults}},
booktitle  = {Proc.~26th IEEE VLSI Test Symp.},
month      = apr,
year       = "2008",
pages      = "329--335"
}

@inproceedings{Shukoor_7_08,
author     = {M. A. Shukoor and V. D. Agrawal},
title      = {{A Primal-Dual Solution to Minimal Test Generation Problem}},
booktitle  = {Proc.~12th IEEE VLSI Design \& Test Symp.},
month      = jul,
year       = {2008},
pages      = {269--279}
}

@inproceedings{Jiang_10_08,
author     = {W. Jiang and V. D. Agrawal},
title      = {{Built-in Self-Calibration of On-Chip DAC and DAC}},
booktitle  = {Proc.~International Test Conf.},
month      = oct,
year       = {2008},
note       = {Paper 32.2}
}

@inproceedings{Yogi08b,
   author  = {N. Yogi and V. D. Agrawal},
   title   = {{Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns}},
   booktitle= {Proc. 17th IEEE Asian Test Symp. (ATS08)},
   month   = nov,
   year    = {2008},
   pages   = {69--74}
}

@inproceedings{Wang09,
   author  = {F. Wang and V. D. Agrawal},
   title   = {{Soft Error Rates with Inertial and Logical Masking}},
   booktitle={Proc. 22nd International Conf. VLSI Design},
   month   = jan,
   year    = {2009},
   pages   = {459--464}
}

@inproceedings{Alexander_03_09,
author     = {J. D. Alexander and V. D. Agrawal},
title      = {{Computing Bounds on Dynamic Power Using Fast Logic Simulation}},
booktitle  = {Proc. 41st Southeastern Symp. System Theory},
month      = mar,
year       = {2009},
pages      = {107--112}
}

@inproceedings{Menon_5_09,
author     = {S. Menon and A. D. Singh and V. D. Agrawal},
title      = {{Output Hazard-Free Transition Delay Fault Test Generation}},
booktitle  = {Proc. 27th IEEE VLSI Test Symp.},
month      = may,
year       = "2009",
pages      = "97--102"
}

@inproceedings{Sindia_5_09,
author     = {S. Sindia and V. Singh and V. D. Agrawal},
title      = {{Polynomial Coefficient Based DC Testing of Non-Linear
Analog Circuits}},
booktitle  = {Proc. 19th IEEE Great Lakes Symp. on VLSI},
month      = may,
year       = "2009",
pages      = "69--74"
}

@inproceedings{Alexander_05_09,
author     = {J. D. Alexander and V. D. Agrawal},
title      = {{Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations}},
booktitle  = {Proc. IEEE Computer Society Annual Symp. on VLSI},
month      = may,
year       = {2009},
pages      = {127--132}
}


@inproceedings{Tudu_5_09,
author     = {J. T. Tudu and E. Larsson and V. Singh and V. D. Agrawal},
title      = {{On Minimization of Peak Power for Scan Circuit during Test}},
booktitle  = {Proc. 14th IEEE European Test Symp.},
month      = may,
year       = "2009",
pages      = "25--30"
}

@inproceedings{Shukoor_5_09,
author     = {M. A. Shukoor and V. D. Agrawal},
title      = {{A Two Phase Approach for Minimal Diagnostic Test Set Generation}},
booktitle  = {Proc. 14th IEEE European Test Symp.},
month      = may,
year       = "2009",
pages      = "115--120"
}

@inproceedings{Jiang_5_09,
author     = {W. Jiang and V. D. Agrawal},
title      = {{Designing Variation-Tolerance in Mixed-Signal
Components of a System-on-Chip}},
booktitle  = {Proc.~International Symp. Circuits and Systems},
month      = may,
year       = {2009},
pages      = {126--129}
}

@inproceedings{Sindia_7_09,
author     = {S. Sindia and V. Singh and V. D. Agrawal},
title      = {{Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing}},
booktitle  = {Proc.~13th IEEE VLSI Design \& Test Symp.},
month      = jul,
year       = {2009}
}

@inproceedings{Yogi_7_09,
author     = {N. Yogi and V. D. Agrawal},
title      = {{BIST/Test-Decompressor Design using Combinational Test Spectrum}},
booktitle  = {Proc.~13th IEEE VLSI Design \& Test Symp.},
month      = jul,
year       = {2009}
}

@inproceedings{Sindia_9_09,
author     = {S. Sindia and V. Singh and V. D. Agrawal},
title      = {{V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-Linear Analog Circuits}},
booktitle  = {Proc.~7th IEEE East-West Design \& Test Symp.},
address    = {Moscow, Russia},
month      = sep,
year       = {2009}
}

@article{Raja_09,
   author  = {T. Raja and V. D. Agrawal and M. L. Bushnell},
   title   = {Variable Input Delay CMOS Logic for Low Power Design},
   journal = {IEEE Trans. on VLSI Systems},
   month   = oct,
   pages   = {1534--1545},
   volume  = {17},
   number  = {10},
   year    = {2009}
}

@inproceedings{Sindia_10_09,
author     = {S. Sindia and V. Singh and V. D. Agrawal},
title      = {{Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients}},
booktitle  = {Proc.~18th IEEE Asian Test Symp.},
address    = {Taichung, Taiwan},
month      = nov,
year       = {2009}
}

@inproceedings{Sindia_1_10,
author     = {S. Sindia and V. Singh and V. D. Agrawal},
title      = {{Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients}},
booktitle  = {Proc.~23rd International Conf. on VLSI Design},
address    = {Bangalore},
month      = jan,
year       = {2010}
}