IEEE Transactions on Industrial Electronics

Volume 43, Number 6, Dec 1996 Access to the journal on IEEE XPLORE IE Transactions Home Page

43.6.1	Mao-Fu Lai, M. Nakano, "Special section on phase-locked loop techniques," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 607-608, Dec 1996. Abstract Link Full Text Abstract: In this issue, a special section on phase-locked loop (PLL) techniques has been organized. This special section was motivated by new developments in PLL circuits and growing interest in using PLL in various applications. There are five papers contributed by researchers in academic and industrial fields which it is hoped will be of interest to readers
43.6.2	Guan-Chyun Hsieh, J.C. Hung, "Phase-locked loop techniques. A survey," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 609-615, Dec 1996. Abstract Link Full Text Abstract: Phase-locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication and motor servo control systems in the past 30 years. Inventions in PLL schemes combined with novel integrated circuit (IC) technology have made PLL devices important system components. The development of better modular PLL ICs is continuing. As a result, it is expected that they will contribute to the improvement in performance and reliability of future communication systems. They will also contribute to the development of higher accuracy and higher reliability servo control systems, such as those involved in machine tools. This paper provides a concise review of the basic PLL principles applicable to communication and servo control systems, gives the configurations of PLL applications and reports a number of popular PLL chips
43.6.3	F. Kobayashi, M. Haratsu, M. Yabumoto, M. Nakano, "Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 616-620, Dec 1996. Abstract Link Full Text Abstract: Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters. The proposed schemes, taking advantage of normal and loadable operations of counters for these operations, provide for gate count savings of about 30%
43.6.4	N. Margaris, P. Mastorocostas, "On the Nonlinear Behavior of the Analog Phase-Locked Loop: Synchronization," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 621, Dec 1996. Abstract Link Full Text Abstract: Not Available
43.6.5	N. Margaris, P. Mastorocostas, Mao-Fu Lai, M. Nakano, Guan-Chyun Hsieh, "On the nonlinear behavior of the analog phase-locked loop: synchronization," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 621-629, Dec 1996. Abstract Link Full Text Abstract: The synchronization, in the presence of time delay, of a nonlinear analog phase-locked loop (PLL) with an analog multiplier as phase detector (PD) and a lag filter is investigated. A nonlinear model for the voltage-controlled oscillator (VCO) is suggested and the sum frequency component at the PD output is taken into account. Simple expressions of the hold-in range of both the main synchronization and the synchronization at the third harmonic are derived. These expressions point out the effect of the time delay and the filter time constant on the hold-in range. Some conclusions of the presented analysis are not anticipated by the PLL classic theory and allow a better understanding of the loop behavior
43.6.6	A. Takano, "Quick-response torque-controlled induction motor drives using phase-locked loop speed control with disturbance compensation," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 640-646, Dec 1996. Abstract Link Full Text Abstract: This paper presents an excellent speed control scheme for induction motor drives. Phase-locked loop (PLL) techniques based on proportional-integral derivative (PID) feedback of the phase difference is employed to provide extremely accurate speed regulation. The quick-response torque control of an induction motor is used to provide better torque characteristics. In addition, a disturbance is estimated by a disturbance observer and the estimated value is fed back to eliminate the disturbance effect on the motor speed. The proposed system combines the precise speed regulation of PLL technique and the advantage of the quick-response torque control, with the insensitivity to disturbance by the disturbance compensation. A phase-plane analysis is used to evaluate the effects of gain coefficients of PID feedback of phase difference. Experimental results are presented to verify the characteristics of the proposed system
43.6.7	J.S. Tepper, J.W. Dixon, G. Venegas, L. Moran, "A simple frequency-independent method for calculating the reactive and harmonic current in a nonlinear load," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 647-654, Dec 1996. Abstract Link Full Text Abstract: A basic criterion that determines the behavior of an active power filter is the method of calculating the reference current. There are many ways of generating this reference, but the methods are generally complex and hard to tune. This paper describes a simple and effective method for calculating the reference current necessary to feed a shunt active power filter to compensate the power factor and harmonic currents generated by a nonlinear load. Simulations and experimental results are presented, showing that the proposed circuit may operate at frequencies ranging from 40 to 65 Hz without adjustment
43.6.8	E. Galvan, A. Torralba, L.G. Franquelo, "ASIC implementation of a digital tachometer with high precision in a wide speed range," IEEE Trans. on Industrial Electronics, vol. 43, no. 6, pp. 655-660, Dec 1996. Abstract Link Full Text Abstract: A common method in adjustable speed drives uses an incremental shaft encoder and an electronic circuit for velocity estimation. The usual method of counting pulses coming from the encoder in a fixed period of time produces a high-precision velocity estimate in the high-speed range. High precision in the low-speed range can be achieved measuring the elapsed time between two successive pulses coming from the encoder. In this paper, a mixed method that combines the best of the two previously mentioned approaches has been implemented using a simple electronic circuit based on one field-programmable gate array (FPGA) and one read-only memory (ROM)