IEEE Transactions on Industrial Electronics 

Volume 36,  Number 1, Feb 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page



36.1.1    T.C.S. Hsia, "A new technique for robust control of servo systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 1-7, Feb 1989.   Abstract Link    Full Text

Abstract: The robust controller has very simple structures and can be divided into two separate parts: a servo controller and an auxiliary controller. The two controllers are designed independently. The function of the auxiliary controller is to cancel out the plant uncertainties directly without the use of the high loop gain principle. Interpretation of robot controller as a signal-synthesis adaptive controller is given. Practical implementation issues of the auxiliary controller are discussed. Simulations of a design example with large parameter uncertainty, nonlinearity, and external disturbance are presented to demonstrate the effectiveness of the design technique. This technique is further tested with success in an experimental study of joint position control of a PUMA 560 robot arm

36.1.2    M.R. Khare, G.N. Garud, "Microprocessor-based thyristorized control system for speed control of coiler motor," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 8-17, Feb 1989.   Abstract Link    Full Text

Abstract: A microcomputer system developed for the real-time speed control of a coiler-motor in a wire rod mill at the Bhilai Steel Plant, India, is discussed. The software permits the dynamic control of the coiler motor speed and also controls the tensionless back-end problem of the wire rod, resulting in considerable reduction in metal loss and production delay. The net annual saving due to introduction of the system is Rs. 6.2 million (around $0.50 million), and since the cost of implementation of the system is Rs. 5.3 million, the pay-back period is only ten months

36.1.3    A. Rahrooh, T.T. Hartley, "Adaptive matrix integration for real-time simulation," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 18-24, Feb 1989.   Abstract Link    Full Text

Abstract: The theory of weak stability of linear multistep methods for real-time simulation of nonlinear systems leads to the design of a class of linear multistep methods with varying coefficients. These methods do not suffer from weak instability and are generally very useful, especially for real-time simulation of stiff nonlinear systems. An adaptive technique for numerical integration that allows the simulation stepsize to be chosen independently of the system eigenvalues is presented. The method tracks most changes in the dynamics of the system, and changes accordingly the integration coefficients to ensure accuracy and stability of the simulation

36.1.4    Chin-Cheng Kau, K.W. Olson, E.A. Ribble, C.A. Klein, "Design and implementation of a vision processing system for a walking machine," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 25-33, Feb 1989.   Abstract Link    Full Text

Abstract: A vision processing system for a six-legged walking machine, the adaptive suspension vehicle, is presented. The vision-processing system consists of a laser range-finder, and vision computer, a terrain-elevation map, and a guidance computer. The range-finder measures the distances from itself to the objects in the scene. The specially designed vision computer processes the range data into a terrain-elevation form and stores the information with time data in a terrain-elevation map. With the real-time elevation information in the map, the guidance computer can select the best footholds for the walking machine in order to maneuver over rough terrain

36.1.5    P.K. Chande, A.K. Ramani, P.C. Sharma, "Modular TMR multiprocessor system," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 34-41, Feb 1989.   Abstract Link    Full Text

Abstract: A tri-module redundant (TMR) multiprocessor system for increased availability to a real-time application is presented. The system incorporates three homogeneous Z-80 based microcomputers, each with necessary analog/digital I/O facilities and global communication hardware. The software design is modular in nature and is, therefore, cost effective and adaptable for expansion to the N-module redundant (NMR) system. The retry mechanism has been employed for recovery from transient faults. The number of retries is programmable, which makes the system adaptable to an application environment. The system has been used to drive a mobile trolley

36.1.6    M. Morimoto, S. Sato, K. Sumito, K. Oshitani, "Single-chip microcomputer control of the inverter by the magnetic flux control PWM method [machine control]," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 42-47, Feb 1989.   Abstract Link    Full Text

Abstract: Single-chip microcomputer control of a pulsewidth-modulated (PWM) inverter for motor drive applications is presented. The PWM pattern generation and the system control of the inverter are achieved by software of the 8-bit single-chip microcomputer. The single-chip microcomputer has a low processing speed and small memory capacity, disadvantages that can be overcome by the magnetic flux control PWM method. The PWM pattern is generated every 90 μs. The memory capacity of the PWM look-up table is less than 2 kbytes. Experimental results show that the motor performances are the same as that of the multichip triangular-sinewave PWM inverter

36.1.7    J.B. Klaassens, "Steady-state analysis of a series-resonant DC-DC converter with a bipolar power flow," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 48-55, Feb 1989.   Abstract Link    Full Text

Abstract: A time-domain analysis for the steady-state model of a series-resonant power interface for both step-up and step-down modes is presented. The exchange of electrical energy between a source and the resonant circuit in order to stabilize the stored electrical energy is defined. The characteristics of a series-resonant converter with bilateral power flow are presented in normalized form, described by the output characteristics. The results obtained in a four-quadrant motor drive illustrate the characteristics of a high-frequency power interface

36.1.8    D.G. Manzer, M. Varghese, J.S. Thorp, "Variable reluctance motor characterization," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 56-63, Feb 1989.   Abstract Link    Full Text

Abstract: A technique to develop a simple, nonlinear dynamic model (from measurements of flux linkage) which captures all of the relevant dynamics of the motor over its entire operating regime is described. A least squares data reduction algorithm that handles the analyses in a natural way to generate bivariate polynomials to approximate the flux linkage is given. Comparisons with a theoretical method and other measurements are presented

36.1.9    J.J. Jozwik, M.K. Kazimierczuk, "Dual sepic PWM switching-mode DC/DC power converter," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 64-70, Feb 1989.   Abstract Link    Full Text

Abstract: A steady-state analysis and experimental results for a dual sepic pulse-width-modulated (PWM) DC/DC power converter for both continuous and discontinuous modes of operation are presented. The converter is dual to a sepic converter, but it can also be derived from a forward converter by replacing one of its rectifier diodes with a coupling capacitor. The circuit acts as a step-down or step-up converter, depending on the value of the ON switch duty cycle. The transformerless version of the converter has a positive DC/DC voltage transfer function. Therefore, the circuit is suitable for distributed power systems. Design equations for all circuit components are derived. Experimental results measured at 100 kHz were in good agreement with theoretical predictions

36.1.10    K.F. Teng, Ping Wu, "PV module characterization using Q-R decomposition based on the least square method," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 71-75, Feb 1989.   Abstract Link    Full Text

Abstract: The determination of solar cell parameters (I-V characteristic) from experimental data was achieved by using the Q -R decomposition technique based on the least squares method, where all data points were considered. The algorithm used a three-parameter equation transformed from the original cell equation of five parameters. This method could be used to analyze the I-V characteristics of photovoltaic (PV) modules of various technologies under the natural conditions of implementation, and to help to establish the best sizing of a PV system and the best adaptation of a PV system to its environment

36.1.11    W. Ahmad, "A simple analogue multiplier with analogue/digital output," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 76-78, Feb 1989.   Abstract Link    Full Text

Abstract: A simple circuit for the four-quadrant multiplication of voltage signals is described. The output of the multiplier is suitable for analog as well as digital applications. Experimental results obtained are in agreement with the theory developed

36.1.12    C.F. Christiansen, R. Battaiotto, D. Fernandez, E. Tacconi, "Digital measurement of angular velocity for speed control," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 79-83, Feb 1989.   Abstract Link    Full Text

Abstract: A digital method to measure angular velocity for machine control applications is described. The method uses a phase-locked loop to multiply the frequency and reject the jitter. The process for measurement is completed in a very short time, providing not only quick readouts, but also information on transient velocity. Since the sampling intervals are fixed, measurement of angular acceleration can be obtained almost immediately

36.1.13    S. Khalaf, M. Zhu, P. Siy, M. Abdelguerfi, "A real-time industrial pattern classification system," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 84-85, Feb 1989.   Abstract Link    Full Text

Abstract: Using the partitioned matrix approach, a parallel hardware architecture for a parametric (Bayes) classifier is designed. The architecture consists of simple, regularly structured processing elements operating in parallel. As a result, the proposed design is suitable for VLSI implementation. A comparative analysis shows that the approach is more efficient and can significantly reduce the cost required for implementing the classifier, while maintaining high speed

36.1.14    Y.C. Liang, V.J. Gosbell, "A versatile switch model for power electronics SPICE2 simulations ," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 86-88, Feb 1989.   Abstract Link    Full Text

Abstract: Using a versatile switch model, a SPICE2 input file containing voltage-controlled hysteresis, nonhysteresis switches, and ideal silicon-controlled rectifiers can be written to perform both steady-state and transient analysis. Two typical power electronics circuits are simulated to demonstrate various aspects of the model

36.1.15    G. Ciccarella, P. Marietti, "Model reference adaptive control of a thermostatic chamber," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 88-93, Feb 1989.   Abstract Link    Full Text

Abstract: The design and the implementation of a model reference adaptive controller for continuous systems are presented. The algorithm has been developed taking into account: (1) the influence of discrete control on the behavior of continuous systems; (2) the possibility of working directly on the continuous representations of the plant and of the reference model; and (3) the need for concurrent implementation of the control software on multiple microprocessor architectures to obtain real-time response. The adaptive control algorithm has been implemented on a personal computer to control a thermostatic chamber. Results derived from this application show the effectiveness of the proposed algorithm

36.1.16    C.H. Rivetta, E.J. Tacconi, "Comments, with reply, on `An adaptive digital pump controller for phase-locked servo systems' by G.-C. Hsieh et al," IEEE Trans. on Industrial Electronics, vol. 36, no. 1, pp. 93-95, Feb 1989.   Abstract Link    Full Text

Abstract: It is shown that the linearized model of the adaptive digital pump controller utilized for studying stability conditions and used in the simulations in a previously published paper (see ibid. vol.34, no.3, p.379-86, 1987) does not agree with the proposed circuit. A reply from the authors of the original paper is also included

IEEE Transactions on Industrial Electronics

  IEEE Transactions on Industrial Electronics 

Volume 36,  Number 2, April 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page



36.2.1    C.F. Hawkins, H.T. Nagle, R.R. Fritzemeier, J.R. Guth, "The VLSI circuit test problem-a tutorial," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 111-116, April 1989.   Abstract Link    Full Text

Abstract: Defect-free integrated circuits (IC) cannot be guaranteed by VLSI circuit manufacturers. Circuit complexity, IC defect anomalies, and economic considerations prevent complete validation of VLSI circuits. These VLSI test problems are especially acute in high-reliability designs and will only worsen as IC circuit size increases. Designers of IC, board, and system projects must be aware of the difficult engineering challenges that are involved in verifying high-quality ICs. The authors discuss these topics and emphasize the need for basic design for testability methods that must be used to alleviate these problems

36.2.2    R.R. Fritzemeier, H.T. Nagle, C.F. Hawkins, "Fundamentals of testability-a tutorial," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 117-128, April 1989.   Abstract Link    Full Text

Abstract: A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testability analysis as a guide to design and test generation is discussed. Algorithms for automatic test-pattern generation are summarized

36.2.3    H.T. Nagle, S.C. Roy, C.F. Hawkins, M.G. McNamer, R.R. Fritzemeier, "Design for testability and built-in self test: a review," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 129-140, April 1989.   Abstract Link    Full Text

Abstract: A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered

36.2.4    M.G. McNamer, S.C. Roy, H.T. Nagle, "Statistical fault sampling," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 141-150, April 1989.   Abstract Link    Full Text

Abstract: Computational requirements often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault coverage value as an estimate of the fault coverage for the total circuit. As an introduction to the application of sampling methods to fault simulation of integrated circuits, the statistical theory behind these sampling methods and proposed augmentations of these methods for improving the precision of the sample fault coverage are presented. Various proposed sampling schemes are applied to example circuit designs, and the results are analyzed

36.2.5    H.T. Nagle, R.R. Fritzemeier, J.E. Van Well, M.G. McNamer, "Microprocessor testability," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 151-163, April 1989.   Abstract Link    Full Text

Abstract: As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed for testability). The authors describe the testing problem for microprocessors, including the various methods of generating test sets and their application by the user. A survey of the testability features of some of today's commercially available microprocessors is presented. Suggestions for testability features for future-generation microprocessors are also discussed

36.2.6    J.J. Arena, "Calculating the effective pattern rate for high-speed board test applications," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 164-174, April 1989.   Abstract Link    Full Text

Abstract: A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board under test

36.2.7    S.-J. Tsai, C.D. Hechtman, "A custom hybrid GaAs driver and sensor device for a high-speed test system," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 175-184, April 1989.   Abstract Link    Full Text

Abstract: A customized hybrid GaAs device has been designed and prototyped that can operate from DC to 100 MHz and above, interface directly with ECL (emitter-coupled logic), TT (transistor-transistor logic), and CMOS components, and handle both the in-circuit and device testing environments. The circuits for both the driver and sensor are delineated, and some of the design issues are discussed. The prototyping of the design into a hybrid IC is explained and experimental performance results are presented

36.2.8    C.W. Branson, "Integrated pin electronic for a VLSI test system," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 185-191, April 1989.   Abstract Link    Full Text

Abstract: Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology

36.2.9    C.D. Hechtman, "In-circuit test fixture [PCB testing]," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 192-196, April 1989.   Abstract Link    Full Text

Abstract: Deficiencies in the conventional in-circuit fixture are presented. A novel fixture is described, and quantitative comparisons are presented. Crosstalk is decreased by 60 dB, and transmission-line matching is possible

36.2.10    E.J. McCluskey, F. Buelow, "IC quality and test transparency," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 197-202, April 1989.   Abstract Link    Full Text

Abstract: It is shown that extremely high single-stuck fault coverage is necessary for high-quality products. Even 100% single-stuck fault coverage may not guarantee adequate quality. Results are presented that extend previous work and show that for high required IC quality, process yield has a negligible effect on required test thoroughness. The extensions consist of: removing the assumption of a one-to-one correspondence between chip defects and single-stuck faults; demonstrating that for high quality levels the dependence of quality on test coverage is linear rather than exponential and that for high yields, the dependence of quality on yield is also linear; and showing that the yield used in the calculations should be functional rather than die yield. The theoretical results are compared with data obtained from measurements at a production IC facility

36.2.11    W.D. Ballew, L.M. Streb, "Incoming test strategy based upon in-process failure and repair costs," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 203-210, April 1989.   Abstract Link    Full Text

Abstract: An economic model is developed that challenges traditional statistical quality control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM failure rates and the lot-to-lot stability. Since current incoming failure rates have fallen two orders of magnitude to below 100 PPM, the model can be used to re-evaluate conventional test strategies in high-volume manufacturing operations. Process variability as measured by statistical process control methods can now be monitored as lot stability and incoming inspection levels are adjusted accordingly

36.2.12    C.F. Hawkins, J.M. Soden, R.R. Fritzemeier, L.K. Horning, "Quiescent power supply current measurement for CMOS IC defect detection," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 211-218, April 1989.   Abstract Link    Full Text

Abstract: Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer test vectors than a stuck-at test set. Individual CMOS ICs from three different fabrication sites had a unique pattern or fingerprint of elevated IDDQ states for a given test set. When IDDQ testing was added to conventional functional test sets, the percentage increase in failures ranged from 60% to 182% for a sample of microprocessor, RAM, and ROM CMOS ICs

36.2.13    P.P. Fasang, "Analog/digital ASIC design for testability," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 219-226, April 1989.   Abstract Link    Full Text

Abstract: The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the problems associated with testing basic circuit configurations for different types of commonly used analog macros. Using the recommended architecture to gain access to control and observation test points in the analog portions of the mixed analog/digital ASIC, a series of analog test tables for several different analog functions have been derived. The analog test procedures are independent of any digital design for testability that might be used in the digital portions of the ASIC. General testing procedures for current analog/digital ASICs are described along with desirable characteristics for testers for this type of circuit

36.2.14    K.D. Wagner, T.W. Williams, "Design for testability of analog/digital networks," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 227-230, April 1989.   Abstract Link    Full Text

Abstract: The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans

36.2.15    J.-C. Lien, M.A. Breuer, "A universal test and maintenance controller for modules and boards ," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 231-240, April 1989.   Abstract Link    Full Text

Abstract: The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute, the number of test buses they control, and the expansion units they use. A simple yet novel circuit, called a test channel, is used in an MMC. The MMC processor can control a test channel by reading/writing its internal registers. Once initialized by the MMC processor, a test channel can carry out most of the testing of a chip. Thus the processor need not deal with detailed test-bus control sequences since they are generated by the test channel. This strategy greatly simplifies the development of test programs. The proposed MMC can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components. Some of its self-test features are presented

36.2.16    M.G. Karpovsky, P. Nagvajara, "Design of self-diagnostic boards by signature analysis," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 241-245, April 1989.   Abstract Link    Full Text

Abstract: The authors present a single-faulty-chip diagnostic technique which requires only two reference signatures for any number of chips on the original board. With this technique, it is possible to reduce substantially the hardware overhead compared to the diagnostic technique based on separate testing of each chip on the board. The technique can be also used for identification of faulty printed boards in a system or for identification of faulty processors in a multiprocessor system

36.2.17    P. Mazumder, J.H. Patel, "An efficient built-in self testing for random-access memory," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 246-253, April 1989.   Abstract Link    Full Text

Abstract: The authors propose a test algorithm for pattern-sensitive faults in large-size RAM with high circuit density. The algorithm tests an n-bit RAM in 195√n time to detect both static and dynamic pattern-sensitive faults over the 9-neighbourhood of every memory cell. A 4 Mb RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms for detecting pattern-sensitive faults. The test speedup has been achieved by writing a test data simultaneously over many cells, and the stored data are tested simultaneously by a parallel comparator and error detector in a read operation. The existing RAM architecture has been modified very little so that the proposed technique can be implemented very easily even in switched-capacitor DRAM (dynamic random-access memory) with low intercell pitch width. The test procedure has also been applied to built-in self-testing (BIST) and is compared with other BIST implementations

36.2.18    S. Mourad, E.J. McCluskey, "Testability of parity checkers," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 254-262, April 1989.   Abstract Link    Full Text

Abstract: Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed

36.2.19    F. Brglez, D. Bryan, J. Calhoun, G. Kedem, R. Lisanke, "Automated synthesis for testability," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 263-277, April 1989.   Abstract Link    Full Text

Abstract: The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability

36.2.20    J.J. Hallenbeck, N. Kanopoulos, J.R. Cybrynski, "The Test Engineer's Assistant: a design environment for testable and diagnosable systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 278-285, April 1989.   Abstract Link    Full Text

Abstract: The Test Engineer's Assistant (TEA) is a set of computer-aided design (CAD) tools that helps the system design engineer meet testability requirements by construction. TEA addresses system design for testability at all levels of the design hierarchy, the lowest level being the board level. The design is represented as a graph where each node indicates a hardware component (or chip on a board) and each arc represents intercomponent connections. Attributes associated with the graph nodes and a set of rules and testing techniques that are incorporated in the tool databases are used to determine the design features that have to be incorporated into the design to meet test and diagnostic requirements. The tool operates on a design using a combination of algorithmic and heuristic techniques. The authors present the design methodology supported by TEA, discuss the techniques used by the TEA tools to obtain solutions for different design for testability requirements, and present an example of the use of TEA with a real system

36.2.21    C. Robach, P. Wodey, "Linking design and test tools: an implementation," IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 286-295, April 1989.   Abstract Link    Full Text

Abstract: A computer-aided test analysis system was designed to appraise the testability of logic systems and to provide the functional specification of the test programs. To provide a helpful tool for both designers and test engineers, it was necessary to fully integrate this tool in a CAD (computer-aided design) system so that testability might be a design parameter and to automate the test-program production. The authors present the link between this tool and the SILVAR LISCO design system

IEEE Transactions on Industrial Electronics

  IEEE Transactions on Industrial Electronics 

Volume 36,  Number 3, June 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page



36.3.1    J.H. Kim, Z. Bien, "An algorithmic approach to fault diagnosis in linear systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 313-320, June 1989.   Abstract Link    Full Text

Abstract: An algorithmic approach for multiple fault diagnosis of linear discrete-time systems is proposed. Based on notions of an expected deviation vector and variation factors, it is shown that t faults in functional units of a dynamic system can be diagnosed with t+1 sample times. The method is considered efficient when the number of faults is unknown but small and when the sampling period is lengthy, as in chemical process with large time constants. Its effectiveness is illustrated by simulated examples

36.3.2    J.-X. Xu, H. Hashimoto, J.-J.E. Slotine, Y. Arai, F. Harashima, "Implementation of VSS control to robotic manipulators-smoothing modification," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 321-329, June 1989.   Abstract Link    Full Text

Abstract: The authors focus on the implementation of a variable structure systems (VSS) controller with smoothing laws in the design of effective tracking control for multi-input, multi-output robotic arms. The controller is realized by selecting powerful smoothing methods, such as balance conditions or their simplification, to reduce or remove undesirable chattering while keeping the robust characteristic that rejects system uncertainties. Giving careful consideration to actual system constraints, a design principle for selecting different smoothing methods is obtained and confirmed by experimental results

36.3.3    W.L. Nelson, "Continuous steering-function control of robot carts," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 330-337, June 1989.   Abstract Link    Full Text

Abstract: Three alternative approaches for eliminating steering discontinuities are presented: changing the steering mechanism, changing the guide-point on the cart, or changing the curves on the path. The first approach requires a steering mechanism that allows the cart to move in any direction without changing its heading. The most common configurations in an automatically guided vehicle are the steered-wheel and differential-drive types. The second approach may be a reasonable choice for differential-drive carts but less so for steered-wheel carts because of their limited maneuverability. For applications where the third approach is preferred, two types of curves providing continuous steering functions for both steered-wheel and differential-drive carts are proposed: Cartesian quintics for lane changes and polar splines for symmetric turns of arbitrary angle. These curves have computationally simple, closed-form expressions that provide continuous curvature and precise matching of the boundary conditions at the line-curve junctions on the paths

36.3.4    C. Umeagukwu, B. Maqueira, R. Lambert, "Robotic acoustic seam tracking: system development and application ," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 338-348, June 1989.   Abstract Link    Full Text

Abstract: The description of an ultrasonic-based seam-tracking robotic system that guides a nonwelding torch along different welding grooves is presented. A 100 kHz airborne transducer is used to inspect the workpiece ahead of a welding torch and measures the joint orientation and lateral deviation caused by curvature or discontinuities in the joint part. Data pertaining to the joint orientation and lateral deviation (echo pulse amplitude and time of flight) are obtained periodically by sampling equi-spaced points along the joint as the torch advances. A trajectory-generating algorithm uses this data to calculate the x, y, &thetas; coordinates of the torch-tip trajectory needed to meet the tracking requirements. The experimental results from a feasibility study conducted to determine if this system could be used for tracking during live welding are also presented

36.3.5    H. Haneda, A. Nagao, "Digitally controlled optimal position servo of induction motors," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 349-360, June 1989.   Abstract Link    Full Text

Abstract: A high-performance optimal position servo is proposed for a microcomputer-controlled induction motor. The servo is designed and realized by top-down computer-aided design (CAD). A field-orientation-control approach is adopted to design an optimal voltage-controlled regulator for position control. A type of globally stable and parameter insensitive observer-linearizer is presented and utilized to overcome the restricted availability of sensed variables: winding voltages and currents, and shaft speed and angle. The digital scheme has been experimentally tested and verified. The effect of quantization errors and sampling period in analog/digital analog on the response and accuracy of the control system is shown

36.3.6    Jong-Hwan Kim, Yeon-Chan Hong, Sung-Jun Lee, Keh-Kun Choi, "Direct adaptive control of nonminimum phase systems using integral action," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 361-364, June 1989.   Abstract Link    Full Text

Abstract: A direct adaptive control scheme is proposed for nonminimum-phase systems in which controller parameters are estimated from the recursive least-squares algorithm and additional auxiliary parameters are obtained from the proposed polynomial identity. A local convergence is guaranteed without any extra condition. Integral action is incorporated into the adaptive controller to eliminate the steady-state error and to satisfy a condition of the unique solution for the polynomial identity. The control law used in this scheme is based on the set-point-on-I-only proportional-integral-derivative (PID) structure

36.3.7    G.-C. Hsieh, "A study on position servo control systems by frequency-locked technique," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 365-373, June 1989.   Abstract Link    Full Text

Abstract: A frequency-pumped controller (FPC) is presented that processes the position servomechanism by the frequency-locked technique. With the proposed FPC, a position/voltage (P/V) transducer, and a voltage-controlled oscillator (VCO), a frequency-locked position servo (FLPS) control system is established. Mathematical models for the FPC and for the FLPS are constructed, and their stability criteria for in-lock and for out-of-lock cases, respectively, are derived. Computer simulation and experimental results confirm the theoretical prediction that the proposed FLPS can provide real-time control, good stability, higher resolution, and higher precision

36.3.8    L.A. Jones, J.H. Lang, "A state observer for the permanent-magnet synchronous motor," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 374-382, June 1989.   Abstract Link    Full Text

Abstract: An identity state observer for the permanent-magnet synchronous motor is derived which reconstructs the electrical and mechanical states of the motor from current and voltage measurements. The observer operates in the rotor frame and estimates direct and quadrature stator currents, rotor velocity, and rotor position. Since the rotor position is estimated, the rotor reference frame is approximated using the latest rotor position estimate. The motor dynamics and the transformation into the estimated rotor frame are nonlinear, and thus the observer and observer error dynamics are nonlinear. Therefore, stability is analyzed using a linearized error model. Simulations including realistic measurement disturbances are used to investigate the global stability and accuracy of the observer

36.3.9    K.C. Cheok, H.X. Hu, N.K. Loh, "Discrete-time frequency-shaping parametric LQ control with application to active seat suspension control," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 383-390, June 1989.   Abstract Link    Full Text

Abstract: The theory of a discrete-time parametric linear quadratic (PLQ) control is extended to a class of frequency-shaped performance measures. The incorporation of frequency-dependent weighting matrices allows the emphasis or de-emphasis of the importance of the system variables being penalized over specific bands of frequencies. Results are presented for constant-gain and dynamic output feedback configurations of frequency-shaping optimal control. The resultant control is applied to the design of active seat suspension control. The active suspension maximizes ride comfort by discriminatory minimization of average whole-body absorbed power over a band of frequencies that causes the most discomfort to a human being

36.3.10    A.P. Jayasumana, G.G. Jayasumana, "On the use of the IEEE 802.4 token bus in distributed real-time control systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 391-397, June 1989.   Abstract Link    Full Text

Abstract: The performance of the IEEE 802.4 priority mechanism in handling distributed real-time control traffic is examined. A timer assignment technique is presented for such applications. The timers are set to satisfy the worst-case access delay requirements of real-time control applications. Other applications that are not time constrained can be supported simultaneously. Under certain conditions, such applications can also be guaranteed a minimum bandwidth allocation. Simulation results are used to evaluate the timer assignment scheme

36.3.11    R.M. Nelms, B.W. Evans, L.L. Grigsby, "Simulation of AC spacecraft power systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 398-402, June 1989.   Abstract Link    Full Text

Abstract: A technique is presented for modeling and simulating AC spacecraft power systems by combining all component models into an overall system model. Each component in the spacecraft power system is treated as a two-port network. A state model is written for each two-port network with the port voltages as the inputs. Each component state model is solved independently using the state transition matrix approach and assuming that its inputs are constant. The inputs to all components are then calculated using network analysis principles. As an example, a 20 kHz system is simulated using this approach, and the results are compared with those of a SPICE2 simulation

36.3.12    B.K. Bose, "Power electronics-an emerging technology," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 403-412, June 1989.   Abstract Link    Full Text

Abstract: The author presents a tutorial review of power electronics and drives in which the status of the technology and its future are discussed. He focuses on power semiconductor devices, converter circuits, AC machine control, and microcomputer applications in power electronics systems. He examines the impact of computer-aided design and artificial intelligence, and he summarizes the technological trends. He predicts that the technology will grow with increasing momentum as component technologies continue to grow

36.3.13    A. Patra, G.P. Rao, "General hybrid orthogonal functions-a new tool for the analysis of power electronic systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 413-424, June 1989.   Abstract Link    Full Text

Abstract: A set of general hybrid orthogonal functions (GHOFs) is introduced to meet the needs of any problem of spectral analysis. The completeness of the set of GHOFs is established, and its flexibility and use for efficient representation of signals in typical practical problems is discussed. The GHOF spectral analysis of linear time-invariant dynamical systems in state space is presented. The technique is applied to two illustrative silicon-controlled-rectifier-controlled DC motor drive simulations, which clearly demonstrates the power of the GHOF in simulating such systems. Some aspects of programming necessary for the related software development are presented

36.3.14    M.K. Kazimierczuk, X.T. Bui, "Class-E DC/DC converters with a capacitive impedance inverter," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 425-433, June 1989.   Abstract Link    Full Text

Abstract: Analysis and design rules are presented for three class-E switching-mode DC/DC power converters, each with a capacitive impedance inverter. Experimental results are given for one of the converters. A zero-voltage switching technique is achieved for both class-E inverters and rectifiers. Therefore, the efficiency of the converters is very high at switching frequencies in the megahertz range. By applying a capacitive impedance inverter, lossless operation of the class-E inverter can be obtained for a wide range of converter load resistance, from full load to infinity. Experimental results are in excellent agreement with the theoretical calculations. Only a 12% relative bandwidth of the switching frequency is required to maintain a constant DC output voltage for the load resistance from full load to infinity at about 1 MHz with 15-W output

36.3.15    M. Sakui, H. Fujita, M. Shioya, "A method for calculating harmonic currents of a three-phase bridge uncontrolled rectifier with DC filter," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 434-440, June 1989.   Abstract Link    Full Text

Abstract: A practical method is proposed for calculating the harmonic currents of a three-phase bridge uncontrolled rectifier with a DC filter, taking into account the AC source reactance. The method is based on the frequency-domain method and the rectifier switching functions. Analytical equations for the harmonic currents on both the DC and AC sides are derived. The validity of the method is demonstrated by comparison with the results of time simulation. The approach can be extended to the harmonic analysis of a thyristor rectifier as well as a rectifier with unbalanced line conditions

36.3.16    S. Martinez, M. Castro, R. Antoranz, F. Aldana, "Off-line uninterruptible power supply with zero transfer time using integrated magnetics," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 441-445, June 1989.   Abstract Link    Full Text

Abstract: An offline uninterruptible power supply (UPS) or emergency power system with zero transfer time is presented. The principal application is to personal computers and systems. The power transformer, a triport-like transformer, acts as an inverter and as a voltage stabilizer with no external loading coil. It is made with commercial EI scrapless laminations. The battery charging circuit is integrated into the transformer and improves the dynamic output response during line-mode operation. The result is robust, short-circuit-proof equipment with harmonic distortion of lower than 3%, a static output stability better than 1.5%, and a very high reliability

36.3.17    C.M. Tan, S. Zukotynski, "Single wafer miniature Hall-effect keyboard," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 446-450, June 1989.   Abstract Link    Full Text

Abstract: A design is proposed for a miniature Hall-effect keyboard for use in hand-held calculators. The keyboard includes a set of MOSFETs as the Hall effect sensors and all the necessary electronic components for keyboard control and communication on a single silicon substrate. Because of the elimination of wire connections to each key-cap and the use of MOSFET circuitry for key sensing, the implementation is expected to lead to high reliability and low power consumption. Some design aspects, including mask layout, and process steps are described

36.3.18    L.J. Giacoletto, "Simple SCR and TRIAC PSPICE computer models," IEEE Trans. on Industrial Electronics, vol. 36, no. 3, pp. 451-455, June 1989.   Abstract Link    Full Text

Abstract: An ideal voltage-controlled switch provided in PSPICE is used to develop simple computer models for silicon-controlled rectifiers (SCRs) and TRIACs. With additional parameters, most of the thyristor properties are modeled. Detailed modeling of the C149M10 SCR and ZN6346A TRIAC and related applications are described

IEEE Transactions on Industrial Electronics

  IEEE Transactions on Industrial Electronics 

Volume 36,  Number 4, August 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page



36.4.1    I.R. Smith, G. Creighton, L.M.C. Mhango, "Analysis and performance of a novel two-phase drive for fan and water-pumping applications," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 530-538, August 1989.   Abstract Link    Full Text

Abstract: The authors describe a novel form of drive, comprising a two-phase induction motor fed by a two-phase inverter, for use in heating, ventilating, demisting, engine-cooling, and water-pumping applications in public service vehicles and passenger cars. A theoretical analysis of the arrangement is presented and a comparison is made between a number of predicted and experimental characteristics for two practical designs. One of these is a fan drive for engine-compartment ventilation and the other a motor-pump drive for a water-cooling system. In both cases, an acceptable range of speed control is achieved (i.e. ±10% of the normal full-load speed of 3300 r/min.), and an accurate prediction of the performance is provided

36.4.2    J. Shiozaki, B. Shibata, H. Matsuyama, E. O'shima, "Fault diagnosis of chemical processes utilizing signed directed graphs-improvement by using temporal information," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 469-474, August 1989.   Abstract Link    Full Text

Abstract: The fault diagnosis algorithms using a signed directed graph (SDG) as a model of the system is useful in the real-time diagnosis of failures that occur in chemical processes. The accuracy of the algorithm has been improved so that it can select the candidates that are most likely to be the real origin of failure, utilizing the time when the measured variables begins to show abnormality as the representation of the dynamic characteristic of the measured variable. The accuracy and speed of the improved algorithm have been examined by its application to data obtained in fault diagnosis experiments on tank-pipeline systems

36.4.3    J. Holtz, U. Boelkens, "Direct frequency convertor with sinusoidal line currents for speed-variable AC motors," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 475-479, August 1989.   Abstract Link    Full Text

Abstract: A novel concept for a static three-phase to three-phase power converter for an AC drive with a unity power factor and reduced harmonics on the line side is presented. The power circuit comprises two back-to-back connected six-pulse bridges having no energy storage elements in the DC link. This permits pulse-width modulation (PWM) control in both bridges while requiring active turn-off semiconductor switches in only one bridge. The line-side harmonics are suppressed by a three-phase second-order filter. The method of predictive optimization is used for the control of the power converter. The complex control structure of the system is based on an online prediction of space vector trajectories. The steady-state operation of the system is exemplified by simulation results

36.4.4    J.L. Duarte, J.F. Aubry, C. Iung, "Current and speed digital control of commutationless DC drives," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 480-484, August 1989.   Abstract Link    Full Text

Abstract: The digital control of commutationless DC drives using a minimal hardware structure is discussed. The authors present a low-cost monochip microcomputer-based control system for speed regulation and current limitation that has no current measurement of a DC motor fed by thyristors in discontinuous current-mode operation. With this system, the speed of the drive is controlled by a classical algorithm using the Z transform. The thyristor firing is synchronized with the power supply and controlled by internal interrupts of the microcomputer. The current limitation is augmented by an estimation algorithm using an experimental simplified model. Results are presented for a 1 kW DC drive

36.4.5    I. Batarseh, C.Q. Lee, "High-frequency high-order parallel resonant converter," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 485-498, August 1989.   Abstract Link    Full Text

Abstract: A novel approach to the analysis of design of a high-order high-frequency LCC-type capacitive coupled parallel resonant converter (PRC-LCC) operated in the continuous-conduction mode is presented. The presence of an additional capacitor in series with the inductance of the conventional PRC results in a converter with more desirable control characteristics. It is shown that, at switching frequencies lower than the resonant frequency, the gain of the LCC-type converter is lower than the grain of the conventional PRC. This facilitates the converter design with a lower turn-ratio transformer and therefore allows for a higher operating frequency. The complete state-plane diagram of the LCC-type converter, from which a set of steady-state characteristic curves is plotted, is given. Various design curves for component value selections and device ratings are given. A design example with computer simulation results is presented

36.4.6    D.M. Vasiljevic, "The design of a battery-operated fluorescent lamp," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 499-503, August 1989.   Abstract Link    Full Text

Abstract: The author presents the design of a battery-supplied fluorescent lamp for automotive, emergency, or portable light sources. Each fluorescent tube has its own driver circuit that exhibits high efficiency (over 80%), simple design, and low cost. The driver circuit operates at a high frequency (50 kHz) and has an electronic ballast control, symmetrical tube driving, and semiresonance ignition. These operating conditions are optimal, and they provide a long tube life and high illumination

36.4.7    H. Nagase, T. Okuyama, J. Takahashi, K. Saitoh, "A method for suppressing torque ripple of an AC motor by current amplitude control," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 504-510, August 1989.   Abstract Link    Full Text

Abstract: The authors examine a thyristor motor torque ripple suppression method that is simple in configuration. A simplified method of calculating motor torque ripple is introduced. This method enables calculation of velocity fluctuation due to torque ripple in the vicinity of the resonant frequency. Calculation results show that operation around the resonant frequency constitutes a problem. The current amplitude control method is effective for suppressing the torque ripple at the resonant frequency. This method detects the velocity fluctuation component and controls the current amplitude to eliminate that component. The velocity fluctuation component is detectable by using a filter that has a differential element. In addition, it is shown that the characteristic of the control system can be calculated with the aid of a Bode diagram, and its effectiveness is confirmed through simulation. From simulation results, this suppression method is found to be effective in reducing the velocity fluctuation to a practical level

36.4.8    L.-S. Shieh, X.-M. Zhao, J.-L. Zhang, "Locally optimal-digital redesign of continuous-time systems," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 511-515, August 1989.   Abstract Link    Full Text

Abstract: The authors present a novel optimal digital redesign technique for finding a dynamic digital control law from the given continuous-time counterpart by minimizing a local quadratic performance index. The quadratic performance index is chosen as the integral of the weighted squared difference between the states of the original closed-loop system and those of the digitally controlled open-loop system at any instant between each sampling period. The developed optimal digital redesign control law enables the states of the digitally controlled open-loop system to match closely those of the original closed-loop system at any instant between each sampling period, and it can easily be implemented using microcomputers with a relatively large sampling period. An illustrative example is presented to demonstrated the effectiveness of the proposed method

36.4.9    K.E. Addoweesh, W. Shepherd, L.N. Hulley, "Induction motor speed control using a microprocessor-based PWM inverter," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 516-522, August 1989.   Abstract Link    Full Text

Abstract: An MC68000, 16-bit microprocessor system was used to generate pulse-width modulation (PWM) voltage waveforms for a three-phase inverter. An MC6840 programmable timer module (PTM) was used to give real-time PWM voltage waveforms at its three outputs. The MC68000 calculates the width of the pulses for only the first quarter cycle and sorts these into a table. The remaining pulses for the complete cycle are generated using the values of the first quarter because there are conditions of quarter and half-wave symmetry. This results in a considerable saving of microprocessing time. The well-known expressions that define the width of regular sampled PWM pulses were modified to be compatible with the timing system. A real-time method of setting the 120° phase shift between the three phases of the pulses using the PTM was developed and showed a good level of accuracy. The PWM inverter was tested with passive impedance and motor loads. With an induction motor load, harmonics of the stator current and voltage of an order lower than the nineteenth and twenty-third were found to be virtually eliminated. The nineteenth and twenty-third harmonics had the value of 0.09 pu of the current, compared with 0.3 for the voltage, at a depth of modulation of unity

36.4.10    P.N. Materu, R. Krishnan, "Steady-state analysis of the variable-speed switched-reluctance motor drive," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 523-529, August 1989.   Abstract Link    Full Text

Abstract: The principle of operation of the switched-reluctance motor (SRM) drive demands that the motor and converter be treated as one unit. Little has been done to develop a complete analysis of this motor-converter combination. The authors present an approach to the steady-state analysis of the drive including the effects of stator winding resistance, input filter parameters, and snubber circuits, which are often neglected. The analysis yields current, voltage, torque, and back-EMF (electromotive force) waveforms that provide guidelines to the optimal design of the drive. Experimental verification is provided for a 6/4 pole prototype SRM drive, and it is shown to be in good agreement with the simulation results. It is noted that this approach can be applied to any other motor-converter combination with minimal modification

36.4.11    G. Amaratunga, K.-W. Kwan, M. Tso, D. Crawley, "A single-chip CMOS IC for closed-loop control of step motors," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 539-544, August 1989.   Abstract Link    Full Text

Abstract: A CMOS integrated circuit for the closed-loop drive of step motors that avoids direct rotor position sensing is reported. The sequencer is integrated with the control circuit. The circuit has been fabricated on a 4 μm gate array, and its operation with the motor and chopper drive is characterized. Dynamic torque-speed characteristics, which are linear up to 85% of the maximum static torque with a 40% increase in power output compared to open-loop operation, have been obtained from a test motor. The CMOS integrated circuit controller makes the use of a step motor a viable alternative to series DC motors. It can be extended to provide a closed-loop drive circuit for step-mode operation

36.4.12    Y.-S. Li, T.Y. Young, C.-C. Huang, "Noncontact measurement using line-scan cameras: Analysis of positioning error," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 545-551, August 1989.   Abstract Link    Full Text

Abstract: A multiprocessor camera controller has been designed and developed for real-time operation of high-resolution industrial CCD (charge coupled device) line-scan cameras. A three-camera system is capable of measuring length, width, height, and volume of steel slabs. Data captured by one camera are made available to other camera processors. A computation scheme is developed to correlate information for accurate cooperative measurement. There are two major sources of measurement errors. Digitizing error has been examined elsewhere, and a 0.1 subpixel accuracy is achievable by appropriate processing. The authors consider positioning errors with emphasis on camera positioning. The cooperative measurement and computation scheme measures object translation and compensates its effect to a certain degree. It is shown that, with calibration, measurement errors caused by camera positioning can be kept error caused by camera positioning can be kept within 0.2%

36.4.13    C. Hutchens, C. Yap, "Continuous background monitoring of plant performance utilizing a single-chip microcomputer and PRTN sequences," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 552-559, August 1989.   Abstract Link    Full Text

Abstract: The authors demonstrate a method suitable for a single-chip microcomputer or VLSI implementation that provides continuous real-time background monitoring of linear electromechanical systems. In this implementation method, pseudorandom noise is generated and digitized with a single-chip microcomputer and utilized to observe shifts in plant performance by monitoring the impulse response. A Butterworth filter was chosen to simulate the electromechanical system for ease and convenience of transfer function modification during testing. The feasibility of monitoring and detecting shifts in plant performance using pseudorandom noise in the background mode in real time while the plant continues to carry out routine control was demonstrated experimentally. Guidelines are provided for selecting the pseudorandom noise amplitude and the analog/digital quantization level. Pseudorandom trinary noise was demonstrated to be superior to pseudorandom binary noise

36.4.14    S. Miyazawa, F. Nakamura, N. Yamada, "A novel strategy for microcomputer-based control of a single-phase output cycloconverter," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 560-567, August 1989.   Abstract Link    Full Text

Abstract: A novel control algorithm using a time process chart that is capable of accurate control of cycloconverters is developed. This algorithm is obtained by making a straight-line approximation in a newly contrived phase plane. In spite of its rather simple procedures, this algorithm is capable of highly accurate control that is comparable to that of the conventional analog scheme. A six-pulse noncirculating current-type cycloconverter is controlled with a small-scale interface and a high-speed control program. Experimental results confirm the validity and usefulness of the proposed method. As far as the processing time is concerned, this method could be used to control a system with a larger pulse number, such as a 12 or 24-pulse system

36.4.15    M.K. Kazimierczuk, J. Jozwik, "Resonant DC/DC converter with class-E inverter and class-E rectifier," IEEE Trans. on Industrial Electronics, vol. 36, no. 4, pp. 468-478, August 1989.   Abstract Link    Full Text

Abstract: A new type of high-frequency high-efficiency resonant DC/DC converter is proposed, analyzed, and verified experimentally. It is called a class-E converter because it consists of a class-E inverter and a class-E rectifier. The class-E rectifier acts as an impedance inverter and is compatible with the class-E inverter. Consequently, the converter can operate with load resistances from a full load to ∞ while maintaining zero-voltage switching of the transistor in the inverter and the diode in the rectifier. It operates safely with a short circuit at the output. Because of a high value of the load quality factor Q1, a narrow frequency range suffices to regulate the DC output voltage over the whole load range. The measured relative bandwidth was δf/fmin=42.2% as the load resistance was varied from 70 Ω to open circuit. The measured efficiency at the full load was 89% with a 9 W output power at 1 MHz. A family of class-E2 resonant DC/DC power converters is given. The possibility of reduction of class-E2 converters to lower-order resonant and pulse-width-modulation converters is shown

IEEE Transactions on Industrial Electronics

  IEEE Transactions on Industrial Electronics 

Volume 36,  Number 5, Oct 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page



IEEE Transactions on Industrial Electronics

  IEEE Transactions on Industrial Electronics 

Volume 36,  Number 6, Dec 1989           Access to the journal on IEEE XPLORE     IE Transactions Home Page