Contact Information:

Spencer Millican

Spencer Millican
Assistant Professor
Auburn University
Department of Electrical & Computer Engineering
341 War Eagle Way
Auburn, AL, 36849-5201
(334) 844-1873
millican@auburn.edu

Office Hours (Fall 2017):

12:00pm-1:00pm Tuesday
1:00pm-2:00pm Wednesday
10:00am-11:00am Thursday
or by appt.

Bio Sketch

Spencer Millican has been an Assistant Professor with the Department of Electrical and Computer Engineering at Auburn University since Fall of 2017. His research and teaching expertise is in the area of computer engineering, VLSI design, electronic design automation (EDA), design-for-test (DFT), hardware security, and intellectual property (IP) protection.

Prof. Millican was previously a member of the staff at the IBM development and manufacturing facility in Rochester, MN from 2015 - 2017. While at IBM, he designed circuit testability hardware and developed solutions to test circuits under 14nm constraints. He developed and deployed built-in self-test (BIST) circuitry for IBM P9 and Z processors. His research interests at IBM were increasing the effectiveness and quality of random tests, especially for the constraints of sub-14nm designs.

Prof. Millican graduated with his Ph.D. from the University of Wisconsin - Madison in 2015 under the guidance of Prof. Kewal Saluja and Prof. Parameswaran Ramanathan. His thesis was on the optimization of system-on-chip (SoC) test schedules under power and temperature constraints both with and without dynamic voltage and frequency scaling (DVFS) and 3D stacked integrated circuit (3DIC/3DSIC) architectures. He also simultaneously pursued the encryption of IP cores for safe distribution and simulation.

Prospective Students

I am currently seeking students who are interested in research in my lab. My current areas of interest span system-on-chip development and test, with particular interests as follows:

  • Encryption of intellectual property digital designs for simulation and verification.
  • Random resistant fault detection.
  • Low-power and low-temperature test.
  • Optimization of test economics.
  • Modeling and detection of faults in sub-14nm technology.

Feel free to contact at my office or through email if you are interested in one of these topics or a similar topic. Funding opportunities are available. 

Recent Publications

[1]  S. K. Millican and K. K. Saluja, “A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 20–25.

[2]  S. K. Millican and K. K. Saluja, “Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling,” in 22nd AsianTest Symposium (ATS), 2013, pp. 165–170.

[3]  S. K. Millican and K. K. Saluja, “Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling,” J. Electron. Test., vol. 30, no. 5, pp. 569–580, Sep. 2014.

[4]  S. K. Millican and K. K. Saluja, “Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits,” in IEEE 21st Asian Test Symposium, 2012, pp. 37–42.

[5]  S. K. Millican and K. K. Saluja, “Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints,” in 2015 28th International Conference on VLSI Design, 2015, pp. 487–492.

[6]  S. K. Millican, P. Ramanathan, and K. K. Saluja, “CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 92–97. (Awarded “Best Paper”)

[7]  S. K. Millican, P. Ramanathan, and K. K. Saluja, “Encrypted Digital Circuit Description Allowing Circuit Simulation,” US9390292 B2, 2016.




Last Updated: 10/9/17 7:17 AM