FPGA Design with Xilinx/Mentor Graphics Tools

This document describes the process or designing and implementing digital circuits in Xilinx FPGAs, using CAD tools from Mentor Graphics and Xilinx. There are two basic approaches to creating the FPGA design.

• Schematic-driven design
  1. Draw a schematic with Mentor Graphics' Design Architect.
  2. Simulate the design with Mentor Graphics' Quicksim II.
  3. Translate the schematic to EDIF Netlist Format.
  4. Compile the design for a specific FPGA with Xilinx' Design Manager.
  5. Resimulate the design with timing parameters in Quicksim II.
  6. Load the compiled design into the FPGA.
• Automatic synthesis from a VHDL model
  1. Design a VHDL model of the circuit.
  2. Simulate the design with Mentor Graphics' ModelSimEE.
  3. Synthesize a circuit from the VHDL model with the Exemplar Leonardo tool.
  4. Compile the design for a specific FPGA with Xilinx' Design Manager.
  5. Resimulate the design with timing parameters in ModelSimEE.
  6. Load the compiled design into the FPGA.
• Mixture of schematic and VHDL components
1. Design and simulate VHDL component models with ModelSimEE.
2. Design and simulate schematic component models with Quicksim II.
3. Generate symbols for each schematic and VHDL model in Design Architect.
4. Create a top-level schematic with these symbols in Design Architect.
5. Perform functional simulation with Mentor Graphics' QSPro.
6. Synthesize the VHDL components as macros in Leonardo.
7. Create an EDIF schematic of the entire design.
8. Simulate the schematic with Quicksim II.
9. Compile the design for a specific FPGA with Xilinx' Design Manager.
10. Resimulate the design with timing parameters in ModelSimEE.
11. Load the compiled design into the FPGA.

The remainder of this document describes these individual steps, focusing on Xilinx FPGA-specific issues and the Xilinx tools. The reader is referred to the tutorials on Design Architect, Quicksim II, and ModelSimEE for further information on using those tools.

NEW:  Xilinx has provided a "Flow Manager" tool, which is a single window from which each stepcan be performed  in the design entry, simulation, and implementation processes described below.  Each Xilinx-provided unix commands described below can be executed by pressing a button in the Flow Manager window and supplying the parameters in the form that appears.

To access the Flow Manager:

1. Start the Mentor Graphics Design Manager from a unix command line with the command: pld_dmgr
2. In the Design Manager "Tools" window, find the flow_mgr icon, and double-click on it.
3. The steps in the design flow are listed in order in the Flow Manager window.

New Auburn Users

• To set up your environment to use the Xilinx/Mentor Graphics tools, run the user-setup program, select the eda (electronic design automation) menu, and then click on the Mentor entry to select it. You must log out and then log back in before this becomes effective.
  
• Never change, delete, move, or copy any Mentor Graphics design file with UNIX commands or Windows File Manager operations. Always use the Mentor Graphics Design Manager program, which is activated by the UNIX shell command: pld_dmgr. This invokes a version that has been tailored to the Xilinx design environment. Refer to the on-line Design Manager Tutorial for information on using the Design Manager.

Schematic Capture for Xilinx FPGAs

Use Mentor Graphics' Design Architect to create, check, and save s chematics as usual, but use the provided Xilinx library for the target device family (xc2000, xc3000, xc4000). Refer the the Design Architect Tutorial for information on schematic drawing. The following differences apply to schematics to be realized in Xilinx FPGAs.

• Invoke Design Architect with: pld_da
• Select the Xilinx Library for the desired FPGA family from the pulldown menu:

  Libraries > XACT_LIB > UNIFIED LIB > XC4000 LIB > BY TYPE

  (It's easier to locate parts when listed "BY TYPE")

• Designate external FPGA pin connections:
  • Select input, output, or I/O pads (IPAD,OPAD,IOPAD) from the "io" submenu.
  • Connect each pad to the circuit through a buffer or flip-flop/latch from the "io", "io_flip-flop", or "io_latch" submenus.
  • Optionally, assign a FPGA pad to a specific pin number (otherwise XACT will select pins automatically):
    1. Select "Change Value" in the Text Palette
    2. Click on PXX in the pad symbol
    3. Enter the pin number (ex. P65)
• To use an external RESET pin, include the STARTUP element from the "general" submenu in the schematic and connect the GSR (global set/reset) output through an OBUF buffer to pad P56.
• To use the on-chip clock generator, include the element OSC4 from the "general" submenu in the schematic. (The 8MHz oscillator output and any TWO others can be used.)

Note:There is no simulation model for the OSC4 element. Therefore, in QuickSim II you must manually force clock signals onto each output of OSC4 to be used by the circuit.

Perform Functional Simulation

Before performing the processes needed to compile a design for an FPGA device, the functionality of the design should be verified through simulation with Quicksim II.

• Before simulating a design with Quicksim II, a design viewpoint must be created with Mentor Graphics Design Viewpoint Editor (DVE). This only needs to be done once for each design; it is not necessart to repeat this after making design changes.

  pld_dve -s design-name xc4000e

  DVE locates schematic in container design-name and creates the viewpoint to use simulation models for an XC4000e family device. (Specify xc3000 or other family in the above command line if the design is to be generated for one of those families.)
  
  

• Simulate with QuickSim II as for other designs. (Refer to the Quicksim II Tutorial for information on digital simulation.) To invoke Quicksim II:

  pld_quicksim design-name

  
  Note: The states of all FPGA flip-flops must be initialized by forcing //globalsetreset to 1 and then back to 0 at the beginning of simulation.

Synthesizing a Circuit from a VHDL Model with Leonardo

Use Mentor Graphics' ModelSimEE tools to model and simulate a design. Refer to the on-line tutorial: Design and Simulation with ModelSimEE. Note that design for synthesis principles should be followed in the development of the model.

After the design has been verified with the ModelSimEE simulator, a circuit is synthesized for the desired Xilinx FPGA architecture using the Exemplar Leonardo synthesis tool.

        Click here for an example of the Leonardo "Quick Flow" Tab

1. Invoke Leonardo via the unix command: leonardo
2. Select the Leonardo "Quick Flow" Tab (the default).
3. Select the VHDL file to be synthesized:
   • Click on the Open File icon below the Open files: box
   • Use the navigator to find and select the file.
4. If desired, change the output file name in the Output File box.
   The default is model.edf, where model is the VHDL source file name.
   The default output format is an EDIF schematic file.
5. In the Technologies box, select the target technology:
• Click on the + button next to FPGA to expand the list of vendors.
• Click on the + button next to Xilinx to expand the list of Xilinx device families.
• Click on the desired Xilinx device family. (Ex.: Xilinx 4000E)
6. Select a specific target device from the pull-down Device list.
7. Select a speed grade for the target device from the pull-down Speed Grade list.
8. If desired, enter a target clock rate in the Clock box. Leonardo will use this clock rate as a design constraing if provided.
9. Check the Insert IO Pads box if the circuit is the top-level chip design.
   Uncheck this box if the circuit is to be a module ("macro") to be incorporated into higher-level designs.
10. Under Optimize for, click on either Area or Delay to select how you wish your circuit to be optimized.
11. Click the Run Flow to perform the synthesis operations.
    The results of each step in the flow will be summarized in the windows to the right.
    The resulting EDIF schematic will be saved in the output file, as described above.
12. To view the synthesized circuit, click on the View Technology Schematic button on the Leonardo menu bar.
13. Exit Leonardo and follow the procedures outlined below to implement the design.

Working with a Mixed VHDL/Schematic Model (Schematic on Top)

To mix VHDL and schematic components in a single model, assuming that the top-level model is a schematic, each component model should be created and debugged via simulation, and then a symbol must be created for each schematic and VHDL component model.  Then these symbols can be instantiated on a sheet and connected to other schematic elements to create the top-level schematic. After synthesizing a circuit from a VHDL model, the synthesized circuit can replace the VHDL model associated with its schematic symbol, and a single schematic model can be generated for the entire circuit.  This schematic can then be mapped onto a FPGA device in the Xilinx Design Manager.

Creating a Schematic Symbol for a VHDL Component

1. Before you begin work, create a logical name for the ModelSimEE initialization file to use in locating your working library via the unix command:: vmap work work  (This need only be done one time.)
2. Compile the VHDL model with the "QuickSim Pro symbol information" switch:  vcom -qspro_syminfo mymodel.vhd
3. Open Design Architect, and from the session window select File > Generate > Symbol
4. In the Generate Symbol Form, enter the following (assume the entity name is "reg_4bit" and the architecture name is "behavior").  Generally, the other entries in this form should be left at their default values.

Click here for an example of the Generate Symbol Form

• Click on "Entity" at the top of the form.
• Library Logical Name:  work
• Entity Name:  reg_4bit
• Architecture Name: behavior  (can be omitted if only one architecture for reg_4bit)
• Click OK

5. In the text palette, click on ADD PROPERTY to associate the EDIF schematic file (to be generated by Leonardo) with this component symbol:

• Property name:  file
• Property value:   reg_4bit.edf

6. Check the symbol by selecting, from the menu bar: Check > With Defaults
7. Save the symbol by selecting, from the menu bar: File > Save Symbol > Default Registration

Functional Simulation Before Synthesis

1. Create a viewpoint for the top-level design (accumulator) for the desired Xilinx technology (xc4000e) using the unix command:
       pld_dve -s accumulator xc4000e
   
2. Invoke the QuickSim Pro (QSPro) co-simulation environment to simulate the mixed schematic/VHDL model using the unix command:
       qspro accumulator
   
3. QuickSim Pro comprises a QuickSim II window and a ModelSim EE window. Since the top level is a schematic, the simulation will normally be controlled from the QuickSim II window, as you would for a "normal" schematic.  If you wish to view signals in a VHDL model, they would be accessed via the ModelSim EE window, as you would a "normal" VHDL model.

Functional Simulation After Synthesis

After synthesizing a schematic for each VHDL component model instantiated in the top-level design, the final schematic can be resimulated and compared to the results obtained before synthesis.  Note that each VHDL component symbol should have a "file" property defining the name of the EDIF schematic created by Leonardo.

1. Create a single EDIF schematic (accumulator.edif) of the entire design via the unix command:
         pld_men2edif accumulator xc4000e
   
2. Convert the EDIF schematic to a Mentor EDDM schematic for use in QuickSim II:
         pld_edif2sim accumulator.edif accumulator xc4000e -m -eddm
   
3. Invoke the QuickSim II simulator as you would on a "plain" schematic.
         pld_quicksim accumulator

Realizing the Design in a Xilinx FPGA

The Xilinx M1 Software "Xilinx Design Manager" (XDM) tool synthesizes an FPGA design from an EDIF or XNF netlist file, producing bitstream files that can be loaded into FPGA devices, and simulation models containing accurate timing parameters. If the design is a VHDL model, a circuit in EDIF or XNF format must be synthesized using Leonardo, as described above.

If the design is in schematic form, it must be converted to an EDIF netlist via the Mentor Graphics ENWRITE (EDIF Netlist Writer) program, using the following unix command (creating file design-name.edif) :

pld_men2edif design-name xc4000e

1. Invoke the Xilinx Design Manager on the EDIF or XNF File

The Xilinx Design Manager (XDM) keeps track of each user project. Each project, in turn, may have one or more design versions, with each having one or more implementation revisions. When used for the first time, the user must define a new project, design version, and design implementation revision as follows:

• Invoke the XDM with the UNIX command: dsgnmgr &
  
  
  
• From the XDM menu bar, select File > New Project
  • Enter the EDIF or XNF file name in the Input Design: box, or use the Browser button to locate your EDIF or XNF file.
  • In the Work Directory box, select a directory to receive the files that will be generated as the design is implemented. Each project requires a unique work directory.
  • Optionally - enter a comment (eg. EE523 Project 5) in the Comment box.
  • Click OK.
• From the XDM menu bar, select Design > New Version
  • Click OK to keep the default version name (ver1).
• From the XDM menu bar, select Design > New Revision
  • Keep the default revision name (rev1).
  • Select a Xilinx part by pressing the Select button and selecting the desired part family, part, package, and speed grade from the pull-down menus in the Part Selector form.
  • Click OK.

2. Use the XDM Flow Engine to Implement the Design

• Open the Flow Engine by clicking on its icon at the left side of the XDM window, or from the XDM menu bar, select Tools > Flow Engine.
  
  
  
• In the Flow Engine window, select Setup > Options and refer to the drop-down lists and "Edit Options" buttons in the "Program Options" window.
  • Implementation - Default should normally be selected, and other default options should be retained. However the  "Edit Options" button allows you to alter the amount of work done to place and route the part, other optimization, and the type of timing reports generated:
  • Logic Level Timing Report - summary of timing and delays between the Map and the Place & Route steps (not usually needed).
    
  • Post Layout Timing Report - summary of timing and delays for the final implementation.
    
  • Simulation - produce a back-annotated EDIF netlist file (time_sim.edn) that can be imported into Mentor Graphics tools for post-layout simulation in Quicksim II, or a structural VHDL model (time_sim.vhd) with timing data in an SDF file (time_sim.sdf) to enable post-layout simulation to be done with ModelSimEE.
    
    • To generate an EDIF netlist to use in Mentor's Quicksim II:
      1. Select Quicksim in the Simulation pull-down list.
      2. Click on the Simulation Edit Options button.
      3. Select the General tab, and from the Simulation Data Options pull-down list, select EDIF.
      4. Select the EDIF tab, and from the CAE Vendor pull-down list, select Mentor.  
      5. Below CAE Vendor, ensure that Retain Hierarchy in Netlist is NOT checked.
      6. Click on OK.
    • To generate a VHDL model for use in ModelSimEE:
      1. Select Modelsim VHDL in the Simulation pull-down list.
      2. Click on the Simulation Edit Options button.
      3. Select the General tab, and from the Simulation Data Options pull-down list, select VHDL.
      4. Click on OK.
         
  • Configuration Data - to program the target Xilinx part.

• Click on the right arrow at the bottom of the Flow Engine to implement the design. The Flow Engine will display all commands in a history window, and show its progress in performing the following steps:
  
  1. Translate - Flatten and convert EDIF to internal NGD (Native Generic Design) format.
     
  2. Map - map the design onto Xilinx FPGA configurable logic blocks (CLBs) and I/O blocks (IOBs).
     
  3. Place & Route - place the CLBs and IOBs into the selected part and route all interconnections between them.
     
  4. Configure - generate a configuration file (bit stream) for programming (configuring) the part.

4. Use the XDM Timing Analyzer To Study The Implemented Design

After the Flow Engine has built a part and generated timing files, invoke the XDM Timing Analyzer by clicking on its icon at the right side of the XDM window, or from the XDM menu bar select Tools > Timing Analyzer.

• To get a summary of the clock frequencies and worst-case delays, click on the Analyze Design Performance button in the toolbar, or from the menu bar select Analyze > Design Performance.
  
  
• To get a summary of delays along all paths in the design, click on the Analyze All Paths button in the toolbar, or from the menu bar select Analyze > All Paths.

Simulate the Implemented Design (VHDL + SDF)

The ModelSimEE simulator can be used in the same manner as for functional simulation to verify the implemented design, which now contains accurate timing parameters. The VHDL file generated by the Xilinx Design Manager is a structural model, built from "simulation primitives" in a Xilinx-supplied VHDL library. Timing data is contained in the SDF file generated by the Xilinx Design Manager.

• Before invoking the ModelSimEE simulator, execute the following unix command (this only needs to be done the first time you use the simulator):

  vmap simprim $XILINX/mentor/data/vhdl/simprim

  This updates your ModelSimEE.ini file to tell the ModelSimEE compiler where to find the library of simulation primitives.
  
  

• Compile the VHDL model with the unix command:

  vcom time_sim.vhd

  NOTE: The Xilinx Design Manager always produces a VHDL file named time_sim.vhd. HOWEVER, the entity name is the same as that of the original model, with architecture name: structural.
  
  

• Invoke the ModelSimEE simulator with the SDF file time_sim.sdf with the unix command:

  vsim -sdftyp time_sim.sdf

  
  

  • Select the appropriate entity and architecture from the displayed list.
    
  • For additional information on the ModelSimEE simulator, refer to the on-line tutorial: Design and Simulation with Quick VHDL.

Simulate The Implemented Design (Backannotated EDIF Netlist)

When the Timing Simulation Data option is selected, the Xilinx Design Manager (XDM) generates a backannotated EDIF netlist file (time_sim.edn) that can be converted to a Mentor Graphics component and design viewpoint containing detailed timing information from the chip. This can be simulated to verify that the design works properly under worst case conditions.

1. Invoke the Mentor Graphics Design Manager with UNIX command:
   

   pld_dmgr.

   
   

2. In the Navigator window, select the backannotated EDIF netlist file: time_sim.edn.
   
   
3. From the Navigator window popup menu, select:
   

   Open > pld_edif2tim

   
   This runs the EDIF netlist reader to create a new Mentor Graphics component from the backannotated EDIF netlist. If your original schematic component name was counter, the new component will be counter_lib/counter.
   
   

4. In the Navigator window, select the new component: counter_lib/counter
   
   
5. From the Navigator popup menu, create a simulation viewpoint by selecting
   

   Open > pld_dve

   
   
   

6. From the Navigator popup menu, invoke Quicksim II by selecting
   

   Open > pld_quicksim

   
   
   

   • Select the "Delay" timing mode in the center of the Quicksim II startup form to get accurate timing data.
   • Click on the Visible button to display timing mode details and select Max delays, so you can study the worst-case timing.
   • If your original design was entirely in schematic form (i.e. no HDL models), you may want to select Cross-probing (back end) in the top-right corner of the Quicksim II startup form to gain access to the signals in your schematic during simulation. This can help you set up the trace window.
   • Click OK at the bottom of the form to start Quicksim.

   
   

7. If you selected "Cross-probing", the Design Viewpoint Editor (DVE) will be opened, along with Quicksim II.
   • Click on the OPEN VIEWPOINT button in the DVE palette, and select counter (your original schematic).
   • Click on the OPEN SHEET button in the DVE palette to display the schematic.
   • Click on signals in the schematic to add them to the Quicksim II trace window.

   
   

8. Repeat the simulation that was used to verify your logic design, but this time noting the various signal delays and timing.

XC4000 Demonstration Board Features

The figure above shows the inputs and outputs available on the Xilinx XC4000 Demo Board. These include the following.

Octal DIP Switch

SW5 General-purpose inputs connected to LCA pins: 19 20 23 24 25 26 27 28

LEDs (CR2,CR1):

LEDs driven by LCA pins: 61 62 65 66 57 58 59 60

7-Segment Display Digits:

CR3 is driven by LCA pins: 39 38 36 35 29 40 44 37

CR4 is driven by LCA pins: 49 48 47 46 45 50 51 41

(Segments are: a b c d e f g pt)4

Configuration DIP Switches (SW4)

PWR - ON to use alternate power supply

MPE - Multiple Program Enable -

SPE - Single Program Enable

M0:M1:M2 - configuration download option

• All ON: Serial PROMs (master serial mode - xchecker cable)
• All OFF: Download (serial slave mode)

RST - reset enable (use with RESET pushbutton)

Pushbuttons:

RESET (SW1) - Resets LCA if SW4-1 is ON and RESET is pressed, controlling Global Set-Reset (GSR) via pin 56.

PROG (SW3) - Controls pin 55 (Program_bar) of LCA. Press to reprogram the chip.

SPARE (SW2) - Extra input connected to header J5.

XChecker Cable Connectors (J1 and J3)

Vcc, GND

CCLK - configuration clock from LCA CCLK pin

DONE - configuration done from LCA DONE pin

DIN - data into LCA DIN pin

PROG - reprogram LCA (connected to PROG button)

INIT -initialize LCA

RST - not connected on demo board

Power Connector:

J2 (Be real careful to check this!)

Power, ground, and Xchecker cable connections for stand-alone XC4003A usage:

Vcc - 2,11,22,33,42,54,64,74

Gnd - 1,12,21,31,43,53,64,76

CCLK - 73 (configuration clock)

DONE - 53 (configuration done)

DIN - 71 (FPGA data in from xchecker/sprom)

/PROG - 55 (low to reprogram the FPGA)

/INIT - 41 (low to reinitialize the FPGA)

RST

Note: /INIT = /PROGRAM = +5v during normal operation (pull up).