EXPLORER LSIM SIMULATOR

LSIM OVERVIEW

Lsim is a multi-signal, multi-level simulator that can support models of different levels of abstraction, ranging from behavioral to structural, including gate, switch and transistor levels. Models can be created as Lsim netlists, VHDL models, or M language models.

Lsim Netlist (extracted from schematic or layout)
- gate-level
- transistor-level
VHDL model
- behavioral/functional
- structural: gate-level
M language model
- behavioral/functional
- structural: gate-level

Example Schematic and Lsim Netlist File

N::
TECH scna20orbit
CELL ckt1
{
	IN in0=1;
	IN in1=2;
	IN in2=3;
	OUT out0=4;

	INST inv01 inv01_i0 I=2   O=17;
	INST and02 and02_i0 I0=1  I1=2 O=9;
	INST and02 and02_i1 I0=17 I1=3 O=14;
	INST or02  or02_i0  I1=14 I0=9 O=4;
}

Lsim Simulation Modes

Behavioral/functional (VHDL, M)
Logic gate (Netlist, VHDL, M)
Switch/transistor (Netlist)
Analog ADEPT mode (Automatic Dynamic Electrical Partitioning of Transistors)
- Most structures use SPICE 2G6 models.
- Translate SPICE to Lsim netlist with StoL tool.
Fault simulation

Notes:
- Any mixture of modes can be used within any circuit.
- Toggle ADEPT & switch mode for any element during simulation.

Timing Constraint Checks

Lsim can check for violations of various timing constraints:

setup time
hold time
cycle time
pulse width
skew

Representation of Logic Signal Values in Lsim

Signal values in Lsim are represented by three components:

Logic state:
- low (L)
- high (H)
- unknown (X) - indicates a value between logic thresholds or a value unable to be determined.
Signal strength: the mechanism used to drive the signal line
- Initial (I) - default condition before simulation begins
- Charged (C) - line driven by stored charge
- Driven (D) - overrides charged node
- Supply (S) - overrides driven node
Weight: represents how strongly the signal is driven
- A weight is specified as a value in the range: 00-31
- Charged strength: weight represents charge storing capacity
- Driven strength: weight represents conductance

Valid combinations of signal state, strength, and weight are given in the following table.

**Signal Value = State + Strength + Weight**
	State
Strength	Low (L)	High (H)	Unknown (X)
Initial (I)	IL00	IH00	IX00
Charged (C)	CL00-CL31	CH00-CH31	CX00-CX31
Driven (D)	DL00-DL31	DH00-DH31	DX00-DX31
Supply (S)	SL31	SH31	SX31

Notes:

Colors are used to represent logic states on the waveform display:
- I = purple dot-dot-dash pattern
- C = green dot pattern
- D = blue dash pattern
- S = red solid pattern
Computation of a signal value depends on the Lsim simulation mode.
- Logic arbitration for modules, gates, switch transistors
- ADEPT arbitration for adept transistors and modules
- ADEPT arbitration for net with adept and logic terminals (Digital strengths converted to Thevenin equivalent with RATIORESIST and then converted to a Norton model)

BASIC SIMULATION PROCEDURE

Invoke Lsim, loading the circuit model and any device models.
Insert probes on signal lines to be toggled and/or monitored.
Supply test vectors to be applied to the circuit inputs.
Run the simulation for a given amount of time.
Study and/or save the simulation results.

INVOKING & EXITING LSIM

Start up Lsim from UNIX:

Functional gate-level simulation of a schematic netlist file ckt1.N, created with Mosis Design Kit standard cells and scna20orbit technology:: Lsim ckt1.N $MGC_HEP/lib/scna20orbit/gdt/scna20orbit_fast.dir/fmods_fast
Normal graphical/interactive mode with a transistor netlist model in file model.N created using scna20orbit technology:: Lsim -l $MGC_HEP/technology/gdt model.N
Batch/noninteractive mode: add the switch -B
Interactive/nongraphics mode: add the switch -text

Start up Lsim from the Lshell popup menu

GDT > Lsim

start

Lsim startup file

model.N

model.i

Exiting Lsim

Exit Lsim

LSIM COMMANDS AND MENUS

The Lsim user interface is shown below. Lsim commands may be issued in three ways:

Select operations from the Lsim command menu.
In this tutorial document, menu selections are indicated by: Submenu > Option
Type commands in the Lsim command line, which is the empty box at the bottom of the Lsim.history Window.
Note: most commands have one-letter abbreviations, called hot keys.
Read and execute commands from a file.
Commands are delimited by semicolons in the file.

DEFINING PROBES

Before beginning a simulation, a set of probes must be defined for the circuit. A probe is a circuit node/test point to be forced to logic/voltage levels and/or monitored during simulation. The signal values of all probed circuit nodes are displayed in one or more waveform or stripchart probe display windows. A Probe Display Window monitoring four probes is shown above.

Probe types

Bit - single terminal
Bus - group of terminals
Memory - memory variables of VHDL/M models
Current - monitor current of leaf-cell terminal (ADEPT mode only)

Defining probes

Probes are automatically assigned to all terminals of the uppermost level of the circuit and are displayed in a Probe Display Window.
Add a bit probe to a window:
- Command: probe node1 node2 ... (Hot key: p)
  Example: Probe nodes a1 and b1 in the current window: probe a1 b1
- Menu:Probes > add bit probe
  (A diaolog box will appear in which to enter the node name.)
Add a bus probe to a window:
- Command: bus bus-name radix node1 node2 ...
  Example: Define a 4-bit address bus, to be displayed in hex:
  bus addr x a[3] a[2] a[1] a[0]
  Example: Combine control signals rw, ds, and as and display in binary
  bus ctrl b rw ds as
- Menu: Probes > add bus probe (Hot key: b)
  - Enter the bus name in the probe name box.
  - Enter the node names in the terminals box.
Add a current probe to a window (ADEPT mode only)

Selecting & deselecting probes

Click on a probe name in the window to toggle it between "selected" and "deselected".
Click on + at the top of the window to select all.
Click on - at the top of the window to deselect all.
Click on Invert to change all Selected to Deselected

Removing probes from a window

Select the probe in the window
From the popup window, select
Lsim Command > Probes > purge probe (hot key: CTRL-P)

Adding & removing probe display windows

Create additional probe display windows by selecting Add display window from the background popup menu. A form will appear for entry of signals to be displayed.
Remove a probe display window by selecting Remove from the popup menu accessed in the frame portion of the window.

APPLYING TEST VECTORS TO PROBES

To test a circuit, bit and bus probes can be forced to specified values at any time during simulation. Repeating clock and pulse trains can also be defined and applied to probes.

To interactively and immediately change the logic value of a single-bit probe (supply-level values), select the probe, then use the menu or hot keys:
- Command: high node-name (Hot key: h)
  Menu:Probes > set probe high
- Command: low node1-name (Hot key: l)
  Probes > set probe low
- Command: unknown node-name (Hot key: x)
  Probes > set probe unknown
Example
```
order in out clk clk_bar   #define order of signals in display window
# case 1
l clk; h clk_bar;     # set initial values
h in; simulate 5;     # set in=1 and run 5ns
l in; simulate 5;     # set in=0 and run 5ns
# case 2
h clk; l clk_bar;
h in; simulate 5;
l in; simulate 5;
```
To interactively change the logic values of a bus/multi-bit probe, select the probe, then use the menu or hot keys:
- Probes > set value (Hot key: k)
Define a clock on probe clk with period 100ns: clockdef clk 100
Repeated logic pulse on probe prb1
lpulse prb1 L H 20 1 2 25 50
- Pulse inactive and active levels: L and H
- Pulse begins: 20ns from now
- Pulse shape: rise=1ns, fall=2ns
- Pulse width = 25ns
- Pulse repeat period = 50ns
Specify non-supply strengths via the force command:
- force DL25 in1 in2
  - Drive probes in1 and in2 low with strength=25
- Menu: Probe > force probe (Hot key: f)
  - Select force state/strength in the popup form
  - Probe must be selected first
- vforce 3.2 in1
  - Force probe in1 to 3.2 volts
- Lsim Command > Probe > force value (Hot key: F)
  Enter force voltage in box
  Probe must be selected first

CONTROLLING EXECUTION OF THE SIMULATION

Simulate for a specified amount of time

Enter the simulate command with the desired simulation time. The following each run the simulation for 5ns:
- simulate 5;
- s 5;
If no time is specified with the simulate command the simulation is run for an amount of time equal to the Current Simulation Interval, which is displayed in the Status Window. The following each run the simulation for the current simulation interval:
- Command: simulate;
- Command: s;
- Menu: Execution > simulate
Change the time value in the Status Window as desired.

Interrupting, resetting, and reinitializing a simulation

Interrupt simulation by pressing CTRL-C
Resume an interrupted simulation:
Reseting the circuit to initial conditions
- Maintain the simulation history:Execution > initialize (hot key: _ )
- Reset time to 0: Execution > reset simulation (hot key: CTRL-\)

GROUPING SIMULATION COMMANDS VIA ALIASES

An alias is a symbolic name for a parameterized sequence of commands. The sequence is executed by entering the alias name as if it were a command. Parameters are specified following the alias name, and are substituted for placeholders in the command sequence.

Defining an alias:
- alias case1 "l clk; h in; s 5; h clk; s 5; l clk; s 5";
- alias case2 "l clk; h $1; s 5; h clk; s 5; l clk; s 5;"
Executing alias commands:

VIEWING RESULTS IN THE PROBE DISPLAY WINDOW

Two display types:
Waveform - timing diagrams
Stripchart - list of logic states
Change display type via Lsim Command Menu:
- Display=>toggle display mode (hot key: w)
  NOTE: You may wish to have two probe display windows, with the same info displayed in both types.
Display/track actual voltage of each probe at time under the cursor via Lsim Command Menu:
Display=>toggle cursor tracking (hot key: CTRL-R)
Waveforms - voltages are displayed
Stripchart - full logic state + strength displayed
Zoom in and out via Lsim Command Menu: Display=>zooming.
Scroll back and forth via scroll bar at bottom of window.

Lsim Debugging Aids

Lsim provides several features to aid in debugging circuit models:

breakpoints
execution tracing
single step
circuit traversal