XILINX FPGA DESIGN WITH AUTOLOGIC II

This demonstration is intended to guide the user in using the Mentor Graphics tools for circuit simulation and design. These tools include QuickVHDL, AutoLogic, Design Architect, Design Manager and the Xilinx utilities. The user will be guided through compiling the design, creating the schematic, simulating the design, and running the design on the XC4003 PLD.

Create a VHDL Model

Create a working directory by typing "mkdir <directory name>" at the Unix command prompt. This will be the directory from which you will run the Mentor Graphics tools.

Type the command "setenv MGC_WD <path>" where path is the path from your root directory to the working directory created in the previous step. You can enter this command in your ".cshrc" file to avoid having to issue the command every time you log on to the computer.

Type the sample file, shown below in Figure 2, into a text editor and save it as "sample1.vhd". This program is a representation of the state diagram shown in Figure 1.

Figure 1 - a simple four state machine

  entity statemachine is
      port(clk, x : in  bit;
           y      : out bit);
  end statemachine;

  architecture datapath of statemachine is
      type state is (state0, state1, state2, state3);
      signal state : states := state0;
  begin
      -- output y based on state
      y <= '1' when state = state0 and x = '1' else '0';
      s:
          process(clk)
          begin
              if clk'event and clk = '0' then
                  case state is
                      when state0 =>
                           state <= state1;
                      when state1 =>
                           state <= state2;
                      when state2 =>
                           state <= state3;
                      when state3 =>
                           state <= state0;
                  end case;
              end if;
          end process;
  end;

Figure 2 - a sample VHDL program

Compile the VHDL Model with QuickVHDL

QuickVHDL is a tool for compiling VHDL code to a simulatable model. After the model has been compiled it can be simulated using the QuickVHDL simulator or loaded into Autologic.

Type "qvlib work" at the Unix command prompt to create a working library. This command will create a directory called "work" that contains all the files needed to simulate the design using QVSim.

Type "qvcom sample1.vhd -synth" to create a synthesizable VHDL model. The model will be stored in the "sample1" directory located directly below the "work" directory created in the previous step.

Note: Do not delete, move, copy, or edit any files located in the "sample1" directory using Unix commands. If you need to delete any files, use the command "qvdel <model name>" from the working directory or use Design Manager to delete them.

Synthesize a Circuit with AutoLogic II

Autologic II is a netlist processor and schematic generator. It synthesizes the model using logic equations and then realizes the equations using logic components from a technology-specific library to build the design. It can also perform various optimizations to the design to save space or maximize performance for the selected technology.

Type "alui" at the Unix command prompt to start AutoLogic II.

Load the VHDL Design Model

Using the mouse, click "File->Open->Design" from the menu bar at the top of the screen.

Select the file "sample1.vhd" from the menu as shown in Figure 3.

Figure 3 - The "Open Design" dialog box

Select the Destination Technology (Xilinx 4000 Family)

Click "Setup->Destination Technology" from the menu bar, select "xc4k/default" from the following list of synthesis libraries displayed in the Destination Technology dialog box, and then click on OK.

	Library/Technology

	sample_lib
	scna20orbit_fast
	scna20orbit_nom
	scna20orbit_slow
	xc4k/default
	altera/default

This will load the Xilinx library to be used in generating the schematic. The Xilinx library contains the logic components necessary to synthesize the design in the XC4003 and other Xilinx 4000-series FPGAs.

Synthesize the Circuit Netlist

Choose the "Synthesize->Synthesize VHDL Design" option from the menu bar at the top of the screen. A dialog box, as shown if Figure 4, will appear on the screen.

Type "work" in the Library test box.
Type "sample1" in the Entity text box.
Type "datapath" in the Architecture text box.
Click on OK or press <Enter> to initiate design synthesization.

This will create an unoptimized netlist of a schematic that can be used to simulate the design.

Figure 4 - The "Synthesize VHDL Design" dialog box

Optimize the Circuit Design

Click "Optimize->Optimize Design" from the menu bar at the top of the screen. A dialog box, as shown in Figure 5, will appear.

Choose "Area" option from the "Optimization Type" menu.
Choose "Low" from the "Area Optimization Options" options.
Click the "OK" button or press <Enter> at the keyboard to begin optimizing the design.

Note: Optimizing for area will create a design that uses the minimum number of logic gates to perform the desired functions of the design.

Figure 5 - The "Optimize Design" dialog box.

Click "Optimize->Optimize Design" once more. This time select the "Add I/O Buffers" option from the dialog box.

Note: Optimizing for IO cells will add input and output buffers to all the lines coming in and out of the design.

Re-optimize for area, but this time select "Map" from the "Area Optimizations Options" options. This will add external IO pads to the input and output ports.

Select "yes" from the "All ports" options.
Select "add" from the "Switch" options.
Click the "OK" button or press <Enter> to begin optimizing the design.

Save the design netlist and/or schematic:

Saving the design will cause Autologic to generate netlist files and (optionally) a schematic. Select "File->Save->Eddm" from the menu bar. The Save Design dialog box, shown in Figure 8, will appear.

Type "sample1" in the "Model Name" text box.
Click on the "generate schematic" option button.
Click on OK or press <Enter> to save the design.

Figure 8 -The "Save Design" dialog box.

When the design is saved, a new directory called "eddm" will be added directly under the working directory. All the files generated by Autologic II will be placed in this new directory. The directory structure is as follows.

		..../working_directory
		   _______|_______
		  |		  |
		/work		/eddm
		  |		  |
		/sample1	/work
				  |
				/sample1_s

Note: Since Autologic II creates these files in memory during operation, all changes will be lost if not saved prior to exiting the program.

View the Design with Design Architect

Design Architect is a tool for viewing schematics created by Autologic and also for editing the schematics. Components can be added or removed from the design. It can also check the design for flaws and generate reports based on the design.

Type "pld_da" at the Unix command prompt to start Design Architect.

Select "Design Sheet" from the toolbox located to the right on the Design Architect window or click "Open->Design Sheet" from the menu bar at the top of the screen. Type "eddm/work/sample1" or select the navigator, as shown in Figure 10, to open the "sheet1" file.

Figure 10 -Navigator dialog box.

This will open the schematic and display it to the screen.

Click "View->All" to view the entire schematic in the window.

Tip: To zoom to a particular area of the design, hold down the middle mouse button and move the mouse from left to right while traveling in a downward direction over the area that you wish to view. Release the button and the area that you selected will display in the window.

Modifying the design:

Click "Libraries->XACT_LIB" from the menu bar at the top of the screen.

Select "Unified" from the libraries selection box on the right side of the screen.

Select the "XC4000 LIB" option from the libraries selection box on the right side of the screen.

Select the "By Type" option from the library selection box at the right of the screen.

Tip: You can add components to the design by selecting the component from the library and placing it in the desired location in the schematic window. When the desired component is selected from the parts selection box, located on the right hand side of the screen, it is automatically attached to the mouse pointer. To add the component, just move the mouse until the highlighted component is over the desired location and click the left mouse button. The component will attach itself to the circuit.

Naming the pads

Note: Before placing pin numbers on the input and output pads, you must determine appropriate pins that you will be using on the Xilinx demonstration board. Place the mouse pointer over the label PXX located on the pad. On the keyboard, press . The label on the pad will be highlighted and a dialog box will appear at the bottom of the screen. Using the mouse, clock the text box and type the desired pin number (Example P61), and then press the key. Figure 11 shows a schematic generated by Autologic II for the sample1 model, with inputs and outputs assigned to pins 67, 68, and 61, respectively.

Figure 11 -Autologic II-generated schematic for sample1

Managing the project

Design Manager is a file management system for the models that you create. You can view, delete,

edit, and manage your models from this tool. You can also start some of the other Mentor Graphics tools from here.

Type "pld_dmgr" at the Unix command prompt to start Design Manager.

Figure 12 - Design Manager interface

Create a Viewpoint with PLD DVE

The PLD DVE program is a tool that creates a viewpoint for the design. These viewpoints are used by QuickSim when simulating the design.

Select the "pld_dve" icon from the "tools" window located on the left side of the screen, and double-click on it to start PLD DVE. A dialog, as shown if Figure 13, will appear.

- Type "eddm/work/sample1" into the "Design Object" text box.

- Select "XC4000" from the "PLD Technology" options.

Click "OK" or press the <ENTER> key to start the viewpoint creation process.

Figure 13 - the PLD DVE dialog box

Simulate the Design with Quicksim II

QuickSim II is a tool that will read the netlist or the schematic of the design and simulate its operation as it it were executing in the chip itself. This is very useful for checking the operation of the design to be sure that it will produce the desired results.

Invoke Quicksim II and load the netlist

Select the "QuickSim II" icon from the "tools" window on the left side of the screen and double-click on it to start QuickSim II. A dialog box, as shown in Figure 14, will appear.

Type "eddm\work\sample1" into the "Design Pathname" text box.
Click "OK" or press <ENTER> to start QuickSim II.

Figure 14 - the QuickSim II dialog box

Display Signals in a List Window

Figure 15 -The Signal dialog box.

Click "Add->List" from the menu at the top of the screen. A dialog, as shown in Figure 15, will appear.
Enter the names of the desired signals, as specified in the VHDL code, into the "Signal" text boxes by placing the cursor over the text box and the typeing the name of the signal
Select the format for viewing from the "Displat Radix" options.
Click "OK" or press the <ENTER> key.
After all of the signals are entered, press <ENTER> at the keyboard and a list window containing the signal names, as shown in Figure 16, will appear. The list window will show the values of the specified signals after the simulation is run.

Figure 16 -The List window.

Create a Force File

Specification of sequences of input stimuli is most conveniently done via a "force file", in which all input stimuli are listed as time-value pairs. Use a text editor to create an ASCII force file similar to the one shown in Figure 16.

 -- initialize values
 force //globalsetreset 1 0
 force x 0 0
 force y 0 0
 force clk 0 0
 force state 0 0
 force //globalsetreset 0 60
 -- start simulation
 force clk 0 60
 force clk 1 80
 force clk 0 100
 force clk 1 120
 force clk 0 140
 force clk 1 160
 force clk 0 180
 force clk 1 200
 force clk 0 220
 force clk 1 240
 force clk 0 260
 force clk 1 280
 force clk 0 300
 force clk 1 320
 force clk 0 340
 force clk 1 360
 force clk 0 380
 force x 1 380
 force clk 1 400
 force clk 0 420
 force clk 1 440
 force clk 0 460
 force clk 1 480
 force clk 0 500
 force clk 1 520
 force clk 0 540
 run 600

Figure 16 - force file for "sample1" model

Running the Simulation and Analyzing the Results

Click "Setup->Force->From File" from the menu bar at the top of the screen. An "Open File" dialog box, as shown in Figure 16 will appear.

Type "force_control" or use the navigator to load the file and press <ENTER>. This will cause the simulator to run the force file. The values of the signals will appear in the list window as illustrated in Figure 17.

Figure 17 - output from simulation

The function of the "sample1" model is to cycle from state to state, assigning a value to the output signal y based on the value of the input signal x. If the value of x is 1 at the time of transition between state 3 and state 0, the value of y will become 1. Otherwise, the value of y is 0.

To check the model for correct output, look at the values of x and y during transition from state to state. The signal y should only equal 1 when x is 1 and state is 0.

Build the XC4003 Chip Design Using the Xilinx Tools

The Xilinx tools are used to prepare the design to be run on the XC4000 demonstration board.

Convert the schematic to Xilinx Netlist Format:

Type "men2xnf8 sample1 -p xc4003apc84-5 -verbose" at the Unix command prompt. This command converts the schematic to an EDIF netlist and then to the Xilinx netlist XNF file.

Create the design and generate a bitstream file:

Type "xmake -x sample1" at the Unix command prompt. This command runs several tools that partition, place, and route the design for the XC4003 PLD. This command also produces a bitstream file, called "sample1.bit", that can be downloaded to the XC4000 demonstration board so that the design can be run on the chip.

Testing the Circuit on the XC4003 Demonstration Board

To test a circuit on the XC4003 Demonstration Board, input/output pins must be connected to switchies and LEDs, respectively, the design downloaded to the board via the Xchecker cable, and then the switches exercized according to produce desired circuit responses.

Connect I/O pins to switches and LEDs

Connect the pins 67 and 68 to a pair of single throw switches.
Connect pin 61 to an LED.

Download the design via the XChecker cable

Copy the bitstream file "sample1.bit" onto a floppy disk.
Find a PC with an installed Xchecker cable.
At the DOS prompt type "cd xchecker"
Type"xchecker sample1.bit". This will start the xchecker program and download the file to the demonstration board.

Exercize the circuit

To simulate the clock toggle the switch connected to pin 68.
Toggle the switch connected to pin 67. The LED should light when the switch is high and the state is 0.