CREATING DESIGNS FOR ALTERA PLDs

Altera EPLDs can be designed with a hardware description language (VHDL, Verilog, AHDL) or by creating a schematic drawing and then compiled into a pattern that can be programmed into an EPLD device. The basic design flow is as follows.

Create a schematic drawing in Mentor Graphics Design Architect.
Simulate the design with Mentor Graphics Quicksim II to verify its functionality.
Generate an EDIF netlist from the schematic with Mentor Graphics EDIF Netlist Writer.
Read the netlist into Altera's MAX+PLUS II compiler.
Select device and output options in MAX+PLUS II.
Compile the design, generating a JEDEC file and an EDIF output file.
Read the EDIF output file with Mentor Graphics EDIF Netlist Reader, create a simulation viewpoint, and resimulate to verify the design.
Load the JEDEC file into a programmer and program the EPLD.

Refer to the Design Architect and Quicksim references for details on schematic drawing and simulation.

Creating a Schematic for an Altera EPLD Design

Create a schematic with parts from ALTERA libraries, using the normal procedures outlined in the Design Architect User Guide, with the following exceptions:

Invoke Design Architect with Altera libraries.

Change to working directory: /home/myname/project
Invoke Design Architect with UNIX command: max2_da
Open a component sheet: /home/myname/project/counter

Access Altera parts libraries via the Library>Altera menu bar entry.

GENLIB - generic gates, flip-flops, etc.
LSTTL BY NAME - equivalent 74LS family functions (alphabetical list)
LSTTL BY TYPE - equivalent 74LS family functions (sorted by function type)
LOGIC MODELING - special models from Logic Modeling (not available on our system)

ALTERA GENLIB Library Parts

Elementary gates with different numbers of inputs:

inv

and2

nand2

nor2

or2

xor2

buf

buf.3so

I/O connectors:

portin

portout

portbi

offpag.in

offpag.out

offpag.bi

Power and ground: vcc, ground
Flip-flops and latches:

dff

dffe

jkff

tff

tffe

latch

Special buffer primitives:

GLOBAL -: force use of global signals: clock, preset, clear, output enable, instead of signals generated with internal logic or driven by ordinary I/O pins.
SCLK -: (Classic, MAX 5000 parts) back compatible with GLOBAL. Use GLOBAL instead.
LCELL -: allocate one logic/macro cell. Produce true/complement of a logic function and feed it back to the AND array.
MCELL -: same as LCELL (back compatible). Use LCELL instead.
TRI -: tri-state buffer to drive a bidirectional pin. (output enable defaults to VCC if not specified).
SOFT -: same as LCELL/MCELL, but allocate logic/macro cell only if needed and eliminate otherwise.
EXP -: (MAX 5000, MAX 7000 parts) inverter driven by AND gate and fed back to AND array, to force use of expander product term. Feed logic only within a single LAB.
CARRY -: (FLEX 8000 parts) designate carry-out logic of a function and acts as carry-in to another. Forces use of special fast carry logic.
CASCADE -: (FLEX 8000 parts) designates cascade-out function of one AND or OR gate and acts as cascade-in to another. AND/OR feeding the cascade primitive is logically ORed or ANDed with the second gate.

Higher-level macro functions:

81mux

8count

8fadd

8mcomp

Identify EXTERNAL chip I/O pins via the PINTYPE property.

Select the "pin" on the portin, portout, portbi connector symbol.

Select ADD PROPERTY from the text palette.
Select PINTYPE in the list of properties and enter the direction value IN, OUT, or IXO in the "value" box.

MAX+PLUS II will infer pin direction from the pin name, if no PINTYPE property has been defined, via the following convention. (However, explicit definition of PINTYPE properties is preferable.)

Begin INPUT pin names with the letters: C,E,I,P,R,S,T,W.
Begin OUTPUT pin names with the letter O.

To assign a function to a specific chip, pin number, or logic cell (LC) number within the EPLD device, add a CHIP_PIN_LC property.

Chip: CHIP_PIN_LC = chipname
Pin number 23 of the chip: CHIP_PIN_LC = chipname@23
Logic cell number 44 in the chip: CHIP_PIN_LC = chipname@LC44

To force a set of functions to be placed in the same area of the chip, or if too large for one area, then on the same chip, add a CLIQUE property and assign the same CLIQUE name to each function of the set.

Assign a function to clique "bob": CLIQUE = bob

Perform Functional Simulation to Verify the Design Functionality

Simulation should be used at two points in the design process. Simulation with the initial schematic or VHDL model should be used to verify the functionality of a design before implementing it in a PLD. After the design has been realized with a specific PLD, it should be resimulated to reverify functionality and to examine timing characteristics.

Mentor Graphics Quicksim II is used to perform both simulations by invoking it on different "viewpoints" of the design: one of the initial functional model and one of the PLD implementation. Mentor Graphics Design Viewpoint Editor (DVE) is used to create these viewpoints before and after compilation of the design into a specific PLD. Before compilation, the viewpoint represents only the functionality. After compilation, the viewpoint contains accurate timing information for the actual implementation in the selected PLD.

Creating the Functional Simulation Design Viewpoint:

Assume Design Architect created component counter in the working directory: /home/myname/project
From the working directory, invoke the Design Manager with UNIX shell command: max2_dmgr
Select the component counter by clicking on it in the navigator window.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_fve. This will run DVE and create a functional simulation viewpoint named altera_fsim in the component directory.
Close the shell window that was opened by this command.

Performing the Functional Simulation:

Assuming that the component is still selected in the Design Manager navigator window from the above step, click on the down arrow to navigate to the component directory and then clicking on the viewpoint altera_fsim to select it.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_qsim. This will invoke Quicksim II on the selected viewpoint.
Follow the normal procedures outlined in the Quicksim II simulation guide to simulate and verify the operation of the design.
After exiting Quicksim II, close the extra shell window.

Invoking Quicksim II from a UNIX command line:

Create the functional simulation viewpoint altera_fsim as described above.
From your working directory, /home/myname/project, invoke Quicksim II on the functional simulation viewpoint with UNIX shell command:

quicksim counter/altera_fsim

Follow the normal procedures outlined in the Quicksim II simulation guide to simulate and verify the operation of the design.

Convert the Schematic to EDIF Format to Import it into MAX+PLUS II

Designs are exchanged between the Mentor Graphics and Altera design environments via EDIF netlist files (Electronic Design Interchange Format - an industry standard). An EDIF netlist representation of a Design Architect schematic is generated with the Mentor Graphics EDIF Netlist Writer (ENWrite).

Conversion procedure:

Assume Design Architect created component: /home/myname/project/counter
From working directory /home/myname/project, invoke the Design Manager with UNIX shell command: max2_dmgr
Select the counter component by clicking on it in the navigator window.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_enw. This will run ENWrite and create design viewpoint named altera_edif, a subdirectory /home/myname/project/counter/max2, and an EDIF netlist file named counter.edf within the new max2 subdirectory.
Close the shell window that was opened by this command.

Note that the MAX+PLUS II compiler can also read and process design models written in VHDL, Verilog, or AHDL (Altera Hardware Description Languate).

Compile the Design with Altera's MAX+PLUS II Compiler

The MAX+PLUS II compiler will import design file(s), synthesize a circuit, map the circuit onto one or more EPLDs, and generate a programming file that can be transferred to a programmer to program the EPLDs. All options and operations in MAX+PLUS II are selected using the pulldown menus. The following procedure assumes that EDIF netlist file /home/myname/project/counter/max2/counter.edf has been created as described above.

Invoking MAX_PLUS II from a UNIX shell:

From working directory /home/myname/project invoke MAX+PLUS II with UNIX shell command: max2win
Open the "project" design files and setup files.

MENU: File > Project > Name
In the popup form, use the navigator to find and click on (or type in the EDIF file name):

Project Name: counter.edf
Files: counter.edf

Click on OK.

Compiling the design for a specific device:

Open the Compiler Window.

MAX+plus II > Compiler

Compiler

Select the EPLD device or family of devices to be used to realize the design.

From MENU: Assign > Device
Select a device family: CLASSIC (or FLEX8000, MAX7000, MAX5000, EPS464)
Select a device. Available devices in Auburn-EE:

FLEX8000 => EPF8282A, EPF8452A, EPF8363A
MAX7000S => EPM7128SLC84-6
MAX7000 => EPM7032, EPM7096
MAX5000 => EPM5128
CLASSIC => EP900/910, EP1800/1810
EPS464 => EPS464

Click OK.

Select a Library Mapping File to translate the EDIF file to MAX+PLUS II internal format:

MENU: Interfaces > EDIF Netlist Reader Settings
For EDIF created from a schematic, Select Vendor: Mentor Graphics
For EDIF file created with Leonardo, Select Vendor: Exemplar
Click on OK.

Enable the EDIF netlist writer to generate an EDIF output file (counter.edo) for timing simulation:

Select MENU: Interfaces > EDIF Netlist Writer
Select MENU: Interfaces > EDIF Netlist Writer Settings
Select Vendor: Mentor Design Architect
Click on OK.

To let MAX+PLUS II automatically fit the design into the "optimum" part

MENU: Device > Auto Device Selection
Move desired devices from "available" to "selected" lists, and move undesired parts out of the "selected" list. (Select each part and use the two arrows to move.
Click on OK.

Determine the type of programmer output file to be generated

MAX+PLUS II automatically generates file part1.pof for use by the Altera programmer. (Parts: EPS464, EPM7032, EPM7096).
Where it can, MAX+PLUS II will also generate a JEDEC file for the AllPro-88 programmer. (CLASSIC parts EP900/1800 and EPM5128)

Click on the START button to compile the design. Errors will appear in the message section of the screen (all messages are also saved in a file. You can select an error message and click on HELP to get more information about each error.

MAX+PLUS II will generate the following files in the component directory.

part1.cnf - binary compiler netlist file
part1.edo - EDIF output file (if enabled)
part1.fit - ASCII file showing pin and LC assignments
part1.hif - hierarchy interconnect file
part1.jed - JEDEC file (if enabled)
part1.mtf - ASCII message text file (all session messages)
part1.pof - programmer object file (for Altera programmer)
part1.rpt - ASCII report file
part1.snf - simulator netlist file (for Altera simulator)

Performing Timing Simulation

Timing simulation can be done on the compiled design to analyze the timing parameters that would be achieved in the actual part. To do this, a new simulation viewpoint must be created for the compiled part from the EDIF output file /home/myname/project/ counter.edo generated by MAX+PLUS II as described above.

Import counter.edo into the Mentor environment with the EDIF Netlist Reader (ENRead)

From working directory /home/myname/project, invoke the Design Manager with UNIX shell command: max2_dmgr
Navigate to /home/myname/project and select the counter.edo file by clicking on it in the navigator window.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_enr. This will run the EDIF Netlist Reader, which will create a new subdirectory ALTERAwithin your project directory, and then create a Mentor Graphics component named counterwithin this subdirectory.
Close the shell window that was opened by this command.

Create a simulation viewpoint for the new component with the Design Viewpoint Editor (DVE)

Invoke Design Manager if not still open from above.
Navigate to /home/myname/project/ALTERA and select the counter component by clicking on it in the navigator window.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_ave. This will run DVE and create a design viewpoint named altera_asimwithin this component subdirectory.
Close the shell window that was opened by this command.

Performing the Timing Simulation:

Assuming that the component is still selected in the Design Manager navigator window from the above step, click on the down arrow to navigate to the component directory and then clicking on viewpoint altera_asim to select it.
Press the right mouse button in the navigator window to produce a popup menu, and select Open > max2_qsim. This will invoke Quicksim II on the selected viewpoint.
In the Quicksim II kernel setup window, select the following options:

Timing Mode = Timing
Timing Option = Max
Delay Scale = Scale Factor
Value = 0.1

Follow the normal procedures outlined in the Quicksim II simulation guide to simulate and verify the operation of the design.
After exiting Quicksim II, close the extra shell window.

Program the EPLD

Logical Devices ALLPRO-88 Programmer(EP900, EP1800, MAX5128)

Copy to floppy disk the JEDEC file created by the MAX+PLUS II compiler: /home/myname/project/counter/max2/counter.jed
On the host PC, change to directory C:\ALLPRO and run program ALLPRO to bring up the menu-driven programmer interface. Select the following:

Device select
Choose library and device
PLD
Altera PLD Libarary
Select the specific device (ex. EP900)
Select the specific package type (ex. 40 pin DIP)
To verify that the EPLD is ready to program, select: Blank check device
Read the JEDEC file (file.jed) from floppy disk.
Program and verify the device by selecting: Program
Select Quit