Improved Inversion
Channel Mobility for 4H-SiC MOSFETs
Following High
Temperature Anneals in Nitric Oxide
G.Y.
Chung a), C. C. Tin a), J.R. Williams a),
K. McDonald b), R.K. Chanana b), R.A. Weller c),
S.T.
Pantelides b), L.C. Feldman b), O.W. Holland e),
M.K. Das e) and J.W. Palmour e)
a) Physics Department, Auburn University, AL 36849
b) Department of Physics and Astronomy, Vanderbilt
University, Nashville, TN 37235
c) Department of Electrical Engineering and Computer
Science, Vanderbilt University, Nashville, TN 37235
d) Solid State Division, Oak Ridge National
Laboratory, Oak Ridge, TN 37831
e) Cree Research Inc., Durham, NC 27713
In
the family of wide band gap materials (silicon carbide, the group III nitrides
and diamond), SiC is the only semiconductor that has a native oxide, and metal-oxide-semiconductor
field effect transistors (MOSFETs) have been fabricated using both 4H- and
6H-SiC. The 4H polytype has higher
bulk carrier mobility [1], and is hence the polytype of choice for power MOSFET
fabrication. However, reported channel mobilities for 4H n-channel, inversion mode devices are substantially lower than for
6H-MOSFETs. For power device applications,
the advantage provided by 4H-SiC of lower epilayer resistance for a given
operating voltage is compromised by the low channel mobility. Schorner, et al. [2] attribute the poorer performance
of 4H devices to a large, broad interface state density located at approximately
2.9eV above the valence band edge in both polytypes. More of these states lie in the band gap for
4H-SiC (Egap ~ 3.3eV) compared to 6H-SiC (Egap ~ 3eV)
where they act to reduce channel mobility through field termination, carrier
trapping and Coulomb scattering. Afanasev,
et al. [3] proposed that interface states in SiC/SiO2 structures
result from carbon clusters at the interface and defects in a near-interface
sub-oxide that is produced when the oxidation process is terminated.
The large interface trap density near the conduction band edge proposed
by Schorner, et al. has been observed experimentally for both n-SiC [4,5]
and p-SiC [6]. Li, et al. [7] originally reported improvements
in the electrical performance of dry oxides on 6H-SiC annealed in nitric oxide
(NO). We have grown oxides on 4H-SiC
using standard thermal techniques [8] and conducted post oxidation anneals
in NO [9]. We find that the interface
state density near the conduction band edge in n-4H-SiC can be reduced to
levels comparable to the interface state density near the conduction band
edge in 6H-SiC. Furthermore, the effective
channel mobility for inversion-mode 4H-SiC MOSFETs improves significantly
following high temperature anneals in nitric oxide.
Results are shown in Fig. 1 for standard
hi-lo (quasi-static) C-V measurements on n-4H-SiC
MOS capacitors following NO passivation anneals of 2hr at 1175oC. “Re-ox” refers to samples that were not annealed
in NO. “Re-oxidation” is a standard wet oxidation termination
step [10] that is carried out at several hundred degrees below the oxidation
temperature of 1100oC in order to reduce the interface state density
near mid-gap for p-SiC/SiO2
[4,10,11]. As shown in Fig. 1, NO
passivation reduces the interface state density significantly. The trap density at 0.1eV below the conduction
band edge decreases by approximately one order of magnitude (from about 2x1013
to 2x1012eV-1cm-2) after NO annealing.
AC conductance measurements performed at Cree Research, Inc. for similar
samples confirm the C-V data presented in Fig. 1.
The
results of mobility measurements for a lateral 4H-SiC MOSFET fabricated with
a dry oxide are shown in Fig. 2. The
device has a peak channel mobility of approximately 30cm2/V-s,
and shows a x14 improvement in peak mobility as a result of the NO passivation
anneal. Similar results are obtained for wet oxide
MOSFETs. Figure 3(a) shows a plot
of drain current versus gate voltage that was used to determine a peak effective
mobility of 5cm2/V-s for a device fabricated with Cree’s standard
dry-wet oxide. Figure 3(b) shows the
improvement in mobility that can be achieved with NO passivation. Drain current - gate voltage characteristics
are also plotted in Fig. 3(b) for the standard and passivated MOSFETs. The standard device exhibits the soft turn-on,
high threshold, and single digit mobility [Fig. 3(a)] typical of 4H-SiC MOSFETs.
However, the MOSFET annealed in NO has a 5V threshold, relatively sharp
turn-on, and a peak channel mobility of 37cm2/V-s.
The
characteristics of both the dry and wet oxide devices are consistent with
a lower interface state density near the conduction band edge. Also, the mobility versus gate voltage behavior
for both the wet and dry oxide devices is similar to that of silicon MOSFETs
[12] with only a 15-20% reduction in mobility at the higher gate voltages
where the devices will typically be operated. However, unlike silicon, the mobilities reported
here for SiC are a much smaller fraction of the bulk mobility (~10% for SiC
compared to ~ 50% for Si). This difference
can be attributed to the fact that, even after NO passivation, the interface
state density near the conduction band edge is still ten times higher for
SiC compared to Si. Full wafer testing
for the wet oxide devices resulted in a yield of 90% and an average effective
mobility of 33cm2/V-s. Furthermore,
every working device on the 3.5cm diameter wafer had a peak mobility greater
than 30cm2/V-s – an indication that the NO passivation process
was very uniform.
Measured
channel mobilities for lateral 4H-SiC MOSFETs fabricated with standard epilayers
and standard thermal oxidation techniques are typically well below 10cm2/V-s. A number of attempts – including the NO passivation
process reported herein – have been undertaken in an effort to improve the
effective channel mobility. Sridevan, et al. [13] reported n-channel mobilities as high as 165cm2/V-s
for deposited oxides subsequently annealed in wet N2 and Ar. Ogino, et al. [14] observed significant improvements
in mobility (as high as 99cm2/V-s) following low dose N implants
into the channel region that were designed to adjust device threshold voltage.
Yano, et al. [15] fabricated MOSFETs with wet thermal oxides grown
on the (1120) face of 4H-SiC and reported effective channel mobilities
of around 30cm2/V-s. However, to our knowledge, our results are
the first to show substantial improvement in the inversion channel mobility
for lateral n-channel MOSFETs fabricated
with standard thermal oxidation techniques and standard 4H-SiC. Whether used separately or in conjunction with
other techniques such as low dose implantation, the NO passivation process
represents significant progress in 4H-SiC MOSFET development.
ACKNOWLEDGEMENTS: This work was supported by DARPA Contract #
MDA972 98-1-0007 and EPRI Contract # W0806905.
Research at Oak Ridge National Laboratory sponsored by the Division
of Material Sciences, U.S. Department of Energy, under contract DE-AC05-00OR22725
with UT-Battelle, LLC.
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